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instruction set in computer architecture

instruction set in computer architecture<br>X86 (based on intel 8086 CPU int1978, Intel family, also followed by AMD)<br><br>ARM (32-bit & 64-Bit, initially Acorn RISC machine)<br><br>MIPS (32-bit & 64-bit by microprocessor without interlocked pipeline stages)<br><br>SPARC( 32-bit & 64-bit by sun microsystem)<br><br>PIC (8-bit to 32-bit microchip)<br><br>uf06e Z80( 8-bit)<br>

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instruction set in computer architecture

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  1. + ComputerArchitectureSE-222

  2. Submitted By Submitteed to TapusheRabaya Toma   Lecturer(Senior Scale) Department of Software Engineering    Daffodil International University Md Riyadh Hasan Id:191-35-423 Ashiqur Rahman Id:191-35-410

  3. InstructionSetArchitecture(ISA) Memoryaddressing,instructions,datatypes,memoryarchitecture,interrupts,exceptionhandling,externalI/O

  4. + InstructionSetArchitecture(ISA) • Servesasaninterfacebetweensoftwareandhardware. • Providesamechanismbywhichthesoftwaretellsthehardwarewhatshouldbedone. Highlevellanguagecode:C,C++,Java, Fortran, compiler Assemblylanguagecode:architecturespecific statements assembler Machinelanguagecode:architecturespecific bitpatterns software instructionset hardware

  5. +WellknowISA’s • X86(basedonintel8086CPUin1978,Intelfamily,alsofollowedbyAMD) • ARM(32-bit&64-Bit,initiallyAcornRISCmachine) • MIPS(32-bit&64-bitbymicroprocessorwithoutinterlockedpipelinestages) • SPARC(32-bit&64-bitbysunmicrosystem) • PIC(8-bitto32-bitmicrochip) • Z80(8-bit)

  6. + InstructionSetDesignIssues • Instructionsetdesignissuesinclude: • Whereareoperandsstored? • registers,memory,stack,accumulator • Howmanyexplicitoperandsarethere? • 0,1,2,or3 • Howistheoperandlocationspecified? • register,immediate,indirect,... • Whattype&sizeofoperandsaresupported? • byte,int,float,double,string,vector... • Whatoperationsaresupported? • add,sub,mul,move,compare...

  7. + ClassifyingISAs Accumulator(before1960): 1-address addAacc acc+ mem[A] Stack(1960sto1970s): 0-address addtos tos+next Memory-Memory(1970sto1980s): mem[A] 2-addressmem[A]+mem[B] 3-addressmem[B]+mem[C] addA,B addA,B,Cmem[A]

  8. + Register-Memory(1970stopresent,e.g.80x86): addR1,AR1 loadR1,AR1 2-address R1+mem[A]mem[A] Register-Register(Load/Store)(1960stopresent,e.g.MIPS): addR1,R2,R3R1 3-address R2+R3 loadR1,R2R1 mem[R2] mem[R1]R2 storeR1,R2

  9. OperandLocationsinFourISA + Classes GPR

  10. +CodeSequenceC=A+BforFourInstructionSets StackAccumulator Register(register-memory) LoadR1,AAddR1,B StoreC,R1 Register (load-store) PushAPushBAddPopC LoadAAddBStoreC LoadR1,ALoadR2,BAddR3,R1,R2 StoreC,R3 memory acc=acc+mem[C] memory R1=R1+mem[C] R3=R1+R2

  11. +StackArchitectures • Instructionset:add,sub,mult,div,...pushA,popA • Example:A*B-(A+C*B)pushA • pushBmulpushApushCpushBmuladdsub A C B B*CA+B*C A*B result A B A*B A*BA C A A A*B A A*B A*B

  12. +Stacks:ProsandCons Pros Goodcodedensity(implicittopofstack)Lowhardwarerequirements Easytowriteasimplercompilerforstackarchitectures Cons Stackbecomesthebottleneck Littleabilityforparallelismorpipelining Dataisnotalwaysatthetopofstackwhenneed,soadditionalinstructionslikeTOPandSWAPareneeded Difficulttowriteanoptimizingcompilerforstackarchitectures – – – – – – – – –

  13. AccumulatorArchitectures • Instructionset: • addA,subA,multA,divA,...loadA,storeA • Example:A*B-(A+C*B) • loadB acc=acc+,-,*,/mem[A] • mulC • addA • storeD • loadA • mulB • subD BB*CA+B*C A+B*C A A*Bresult

  14. Accumulators:ProsandCons Pros ● • Verylowhardwarerequirements • Easytodesignandunderstand Cons ● • Accumulatorbecomesthebottleneck • Littleabilityforparallelismorpipelining • Highmemorytraffic

  15. Memory-MemoryArchitectures • Instructionset:(3operands)(2operands) addA,B,C subA,B,C mulA,B,C addA,BsubA,B mulA,B • Example:A*B-(A+C*B) • 3operands • mulD,A,B • mulE,C,B • addE,A,E • subE,D,E • – • – 2operandsmovD,AmulD,BmovE,CmulE,BaddE,AsubE,D

  16. Memory-Memory:ProsandCons • Pros • Requiresfewerinstructions(especiallyif3operands) • Easytowritecompilersfor(especiallyif3operands) • Cons • Veryhighmemorytraffic(especiallyif3operands) • Variablenumberofclocksperinstruction • Withtwooperands,moredatamovementsarerequired

  17. Register-MemoryArchitectures • Instructionset: • Example:A*B-(A+C*B) loadR1,AmulR1,BstoreR1,DloadR2,CmulR2,BaddR2,AsubR2,D R1=R1+,-,*,/mem[B] /*A*B */ /*C*B /*A+CB /* */ */ AB-(A+C*B)*/

  18. Memory-Register:ProsandCons Pros ● • Somedatacanbeaccessedwithoutloadingfirst • Instructionformateasytoencode • Goodcodedensity Cons ● • Operandsarenotequivalent • Maylimitnumberofregisters

  19. Load-StoreArchitectures • Instructionset: addR1,R2,R3 loadR1,&A subR1,R2,R3mulR1,R2,R3 storeR1,&AmoveR1,R2 • Example:A*B-(A+C*B)loadR1,&A • loadR2,&BloadR3,&C R3=R1+,-,*,/R2 mulR7,R3,R2addR8,R7,R1mulR9,R1,R2subR10,R9,R8 /*C*B */ /*A+C*B*/ /*A*B */ /*A*B-(A+C*B)*/

  20. Load-Store:ProsandCons Pros Simple,fixedlengthinstructionencodingsInstructionstakesimilarnumberofcyclesRelativelyeasytopipelineandmakesuperscalar ● ● ● Cons Higherinstructioncount NotallinstructionsneedthreeoperandsDependentongoodcompiler ● ● ●

  21. + Classificationofinstructions 4-addressinstructions 3-addressinstructions 2-addressinstructions 1-addressinstructions 0-addressinstructions

  22. + Classificationofinstructions (continued…) The4-addressinstructionspecifiesthetwosourceoperands,thedestinationoperandandtheaddressofthenextinstruction

  23. + Classificationofinstructions (continued…) A3-addressinstructionspecifiesaddressesforbothoperandsaswellastheresult

  24. +Classificationofinstructions (continued…) A2-addressinstructionoverwritesoneoperandwiththeresult Onefieldservestwopurposes • A1-address instruction hasa dedicatedCPUregister, calledthe accumulator,to holdoneoperand &theresult –No address isneededto specifytheaccumulator opcode source2

  25. + Classificationofinstructions (continued…) A0-addressinstructionusesastacktoholdbothoperandsandtheresult.OperationsareperformedbetweenthevalueonthetopofthestackTOS)andthesecondvalueonthestack(SOS)andtheresultisstoredontheTOS op code

  26. + Comparisonofinstructionformats Asanexampleassume: thatasinglebyteisusedfortheopcode thesizeofthememoryaddressspaceis16Mbytes asingleaddressablememoryunitisabyte Sizeofoperandsis24bits Databussizeis8bits

  27. + Comparisonofinstructionformats • Wewillusethefollowingtwoparameterstocomparethefiveinstructionformatsmentionedbefore • Codesize • Hasaneffectonthestoragerequirements • Numberofmemoryaccesses • Hasaneffectonexecutiontime

  28. Codesize=1+3+3+3+3=13bytes Noofbytesaccessedfrommemory13bytesforinstructionfetch+ 6bytesforsourceoperandfetch+ 3bytesforstoringdestinationoperandTotal=22bytes

  29. +3-addressinstruction Codesize=1+3+3+3=10bytes Noofbytesaccessedfrommemory10bytesforinstructionfetch+ 6bytesforsourceoperandfetch+ 3bytesforstoringdestinationoperandTotal=19bytes

  30. +2-addressinstruction Codesize=1+3+3=7bytes Noofbytesaccessedfrommemory7bytesforinstructionfetch+ 6bytesforsourceoperandfetch+ 3bytesforstoringdestinationoperandTotal=16bytes

  31. +1-addressinstruction opcode source2 1byte 3bytes Codesize=1+3=4bytes Noofbytesaccessedfrommemory4bytesforinstructionfetch+ 3bytesforsourceoperandfetch+ 0bytesforstoringdestinationoperandTotal=7bytes

  32. +0-addressinstruction opcode 1 byte Codesize=1=1bytes #ofbytesaccessedfrommemory1bytesforinstructionfetch+ 6bytesforsourceoperandfetch+ 3bytesforstoringdestinationoperandTotal=10bytes

  33. +Summary

  34. + Example2.1text expressionevaluationa=(b+c)*d -e

  35. https://en.wikipedia.org/wiki/Instruction_set_architecturehttps://www.computerhope.com/jargon/i/instset.htmhttps://en.wikipedia.org/wiki/Instruction_set_architecturehttps://www.computerhope.com/jargon/i/instset.htm

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