Memory Management - III

1. CS423UG Operating Systems Memory Management - III Indranil Gupta Lecture 15 Sep 28, 2005

2. Agenda • Page Tables and TLB • Multi-level Paging • Inverted Page Table • Protection CS 423UG - Operating Systems, Indranil Gupta

3. Virtual-To-Physical Lookups • Programs only know virtual addresses • The page table can be extremely large • Each virtual address must be translated • Page table stored in memory • So, each program memory access requires several actual memory accesses CS 423UG - Operating Systems, Indranil Gupta

4. PTBR=Page Table Base Register (in hardware) CPU Virtual Memory Virtual Address (003006) PTBR=001 003 Page Table 003 006 0 006 4 1 Contents(3006) 0 003, 004 1 1 0 Physical Memory 1 004 006 004 Physical Address (F,D) Page size 1000 Number of Possible Virtual Pages 1000 Number of Page Frames 8 006 Contents(4006) CS 423UG - Operating Systems, Indranil Gupta

5. Address Translation: Birth to Death Virtual address (P,D) 1 (PTBR,P*4)=phy. address of page table entry (4 B per entry) CPU 2 PTBR Return via address bus 3 6 Get page table entry (P,F) (F,D) 4 Access (F,D)’th byte of phy. memory Physical address 5 CS 423UG - Operating Systems, Indranil Gupta

6. Review • Storage management • Bitmap or link list • Compaction • Best fit, quick fit, first fit, next fit, worst fit • Virtual Memory • Paging • Page fault • So … accessing a memory element requires accessing memory TWICE. Expensive! CS 423UG - Operating Systems, Indranil Gupta

7. VPage # Solution: Translation Look-aside Buffer (TLB) Virtual address offset VPage# PPage# ... Real page table Miss VPage# PPage# ... . . . VPage# PPage# ... TLB Hit PPage # offset Physical address CS 423UG - Operating Systems, Indranil Gupta

8. TLB Function • If a virtual address is presented to MMU, the hardware checks TLB by comparing all entries simultaneously (in parallel). • If match is valid, the PTE is taken from TLB without going through page table. • If match is not valid: • MMU detects miss and does an ordinary page table lookup. • It then evicts one entry out of TLB and replaces it with the new entry, so that next time that PTE is found in TLB. CS 423UG - Operating Systems, Indranil Gupta

9. Page Mapping Hardware Virtual Memory Address (P,D) PTBR=001 Page Table P D Associative Look Up 0 P 1 P F 0 First 1 P, F 1 0 TLB (Associative Memory) 1 F D Physical Address (F,D) To main memory CS 423UG - Operating Systems, Indranil Gupta

10. What if Frame number changed in page table? Virtual Memory Address (P,D) PTBR=001 Page Table 003 006 Associative Look Up 0 1 12 4 1 3 6 9 0 19 3 First 1 003, 009 3 7 1 0 TLB (Associative Memory) 1 009 006 Physical Address (F,D) CS 423UG - Operating Systems, Indranil Gupta

11. Page Mapping Example: next reference Virtual Memory Address (P,D) Page Table 003 006 Associative Look Up 0 1 12 4 1 3 9 0 19 3 First 1 003, 009 3 7 1 0 TLB (Associative Memory) 1 009 006 Physical Address (F,D) CS 423UG - Operating Systems, Indranil Gupta

12. Bits in a TLB Entry • Common (necessary) bits • Virtual page number: match with the virtual address • Physical frame number: translated address • Valid bit (if this bit is 0, then TLB entry is invalid) • Access bits: kernel and user (nil, read, write) • Optional (useful) bits • Process tag • Modify • Cacheable CS 423UG - Operating Systems, Indranil Gupta

13. Paging Implementation Issues • TLB can be implemented using • Associative registers • Look-aside memory • Metric: TLB hit ratio (Page address cache hit ratio) • Percentage of time PTE found in associative memory CS 423UG - Operating Systems, Indranil Gupta

14. Hardware-Controlled TLB • On a TLB miss (different from page fault) • Hardware loads the PT Entry into the TLB • Need to write back if there is no free entry • Generate a fault if the page containing the PT Entry is invalid • VM software performs fault handling • Restart the faulting instruction • On a TLB hit, hardware checks the valid bit • If valid, pointer to page frame in memory • If invalid, the hardware generates a page fault • Perform page fault handling • Restart the faulting instruction • Cheap! CS 423UG - Operating Systems, Indranil Gupta

15. Software-Controlled TLB • On a miss in TLB, VM software • Bring PTE, write back victim PTE to memory • Check if the page containing the PT Entry is in memory • If no, perform page fault handling • Set valid bit for PTE in TLB • Restart the faulting instruction • On a hit in TLB, the hardware checks valid bit • If valid, pointer to page frame in memory • If invalid, the hardware generates a page fault • Perform page fault handling • Restart the faulting instruction • Example: RISC including SPARC, Alpha, MIPS, HP PA CS 423UG - Operating Systems, Indranil Gupta

16. Hardware vs. Software Controlled • Hardware approach • Efficient • Inflexible • Need more space for page table • Software approach • Flexible, e.g., can change prefetching policies • Software can do mappings by hashing • PF#  (Pid, VP#) • (Pid, VP#)  PF# • Can deal with large virtual address space • Simpler hardware (frees up chip space for caches!) CS 423UG - Operating Systems, Indranil Gupta

17. Issues • Which TLB entry to be replaced? • Random • Least Recently Used (LRU) • What happens on a context switch? • Process tag: change TLB registers and process register • No process tag: Invalidate the entire TLB contents • What happens when a page table entry is changed? • Change the entry in memory • Invalidate the TLB entry CS 423UG - Operating Systems, Indranil Gupta

18. Effective Access Time • TLB lookup time =  time unit • Memory cycle -- m microsecond • TLB Hit ratio --  • Effective access time • EAT = (1m+)(2m+)(1-) • EAT = 2m+-m CS 423UG - Operating Systems, Indranil Gupta

19. Multilevel Page Tables • If page table is paged, size of process is limited • Since the page table can be very large, one solution is to use hierarchical page tables (think for a minute what this means) • Divide the page number into • An index into a page table of second level page tables • A page within a second level page table • Advantage • No need to keeping all the page tables in memory all the time • Process sizes can be very large CS 423UG - Operating Systems, Indranil Gupta

20. Multiple-Level Page Tables Virtual address pte dir table offset offset . . . offset Directory . . . . . . . . . CS 423UG - Operating Systems, Indranil Gupta

21. Example Addressing on a Multilevel Page Table System • A logical address (on 32 bit machine with 4k page size) is divided into • A page number consisting of 20 bits • A page offset consisting of 12 bits • Divide the page number into • A 10-bit page number • A 10-bit page offset CS 423UG - Operating Systems, Indranil Gupta

22. Multilevel Paging and Performance • Since each level is stored as a separate table in memory, converting a logical address to a physical one in a four-level paging may take five memory accesses. • Why? • Solution? More TLB’s? No, that’s too much hardware. CS 423UG - Operating Systems, Indranil Gupta

23. Inverted Page Tables Physical address Virtual address • Main idea • One page table for all process pages that are phy. memory • No separate page tables for individual processes • One PTE for each physical page frame • Trade off space for time • Pros • Small page table for large process address space • Cons • Lookup is difficult • Overhead of managing hash chains, etc pid vpage offset k offset 0 pid vpage k n-1 Inverted page table CS 423UG - Operating Systems, Indranil Gupta

24. Inverted Page Table Virtual Address (009006) Page Table 009 006 0 1 4 0 1 1 9 0 1 004 006 Physical Address (004006) CS 423UG - Operating Systems, Indranil Gupta

25. Inverted Page Table Implementation • TLB is same as before • TLB miss is handled by software • In-memory page table is managed using a hash table. Hash (pid, page #) to find right entry • Number of entries = number of physical frames • Not found: page fault Virtual page Physical page Hash table CS 423UG - Operating Systems, Indranil Gupta

26. Sharing Pages • Code and data can be shared among processes • mapping them into pages with common frame numbers (i.e., several (*,F) mappings in page tables exist for given F) • Code and data must be position independent if VM mappings for the shared data are different • Code and data cannot store VM addresses for functions and variables not in shared pages CS 423UG - Operating Systems, Indranil Gupta

27. Shared Pages CS 423UG - Operating Systems, Indranil Gupta

28. Incorrect Sharing Physical Memory Virtual Memory 1 Virtual Memory 2 Load(3,5) Load(3,5) 5 Load(3,5) 1 1 6 $100 $20 2 $20 $20 7 3 $100 3 8 CS 423UG - Operating Systems, Indranil Gupta

29. Protection • Can add read, write, execute protection bits to page table to protect memory • Check is done by hardware during access • Shared memory location • Different protections for different processes • Alternative, more Expressive Solution: • Associate protection lock with page frame. Each process has its own key. If the key fits the lock, the process may access the page frame CS 423UG - Operating Systems, Indranil Gupta

30. Protection • Typically many different keys can fit a lock using a priority numbering scheme • e.g., Key 3 fits all locks 3, 7, 15. Key 4 fits 5,6,7,12,13,14,15. CS 423UG - Operating Systems, Indranil Gupta

31. Keys and Locks Process B Keys Page Frames Process A CS 423UG - Operating Systems, Indranil Gupta

32. Reminders • Reading so far: Sections 4.1-4.3 • Reading for next lecture: Section 4.4 • MP2 is out – Deadline October 17, 2004 • HW3 – due THIS Friday. • Midterm: October 10, Monday, 10am-10:50am, 1404 SC CS 423UG - Operating Systems, Indranil Gupta