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Timing Bug in CSC Digis

Timing Bug in CSC Digis. Affected both wire and comparator digis Made BX resolution too good Bug was in expressions like int bx = static_cast<int>( correctedTime / theBunchSpacing ) So everything from t=-24.999 ns to t=+24.999 ns went into BX = 0 Probably existed since ORCA days

albertagibson
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Timing Bug in CSC Digis

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  1. Timing Bug in CSC Digis Affected both wire and comparator digis Made BX resolution too good Bug was in expressions like int bx = static_cast<int>( correctedTime / theBunchSpacing ) So everything from t=-24.999 ns to t=+24.999 ns went into BX = 0 Probably existed since ORCA days Fix submitted to 1_8_0 and 2_0_0.

  2. Effects on Triggering • Under investigation now • In earlier TF, a digi 1 BX early could ruin global muon trigger! • New TF logic will be in 1_8_0 • Now we tune timing to center digis on tbin=6 • Before, we had to err towards later BX.

  3. Wire Digi BX, Old

  4. Wire Digi BX, New

  5. Comparator Digi BX, Old

  6. Comparator Digi BX, New

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