High Speed and Low Power Analog to Digital Data Converters for UWB

1. High Speed and Low Power Analog to Digital Data Converters for UWB By: Ali Mesgarani Electrical and Computer Engineering University of Idaho

2. Outline • Motivation and goals • Background • New ADC topologies proposed for high speed, low power and medium resolution • Asynchronous binary search ADC • Pipeline binary search ADC • Conclusion

3. Motivation • ADCs are key design blocks in modern microelectronic systems. • More signal-processing functions are implemented in the digital domain. • Noise immunity • Low power • Easy to design using CAD tools • Reproducibility, … • Today’s high speed communication systems have increased the demand for increased data rates, small area, and low power consumption. • High speed ADCs have significant importance in today’s digital signal processing and communication systems. • Designing energy efficient A/D converters by developing new architectures and circuits to take full advantage of what the modern process technologies have to offer.

4. Outline • Motivation and goals • Background • New ADC topologies proposed for high speed, low power and medium resolution • Asynchronous binary search ADC • Pipeline binary search ADC • Conclusion

5. Why do we need A/D converters? • The real world is analog, but easier to process digital data. • Speech, image, … • Digital data needs to be carried on an analog signal • Signal received at the antenna must be digitized. • Analog signals contain too much unnecessary amount of data • ADC samples the data and splits it into finite information • ADC converts analog information to digital information

6. ADC at receiver in a link ADC DAC

7. Analog to digital converter (ADC)

8. Quantization 111 110 101 100 Digital Output 011 010 001 000 1 2 3 4 5 6 7 8 Time

9. High speed ADC applications • Ultra Wide Band (UWB) communication • High Speed Serial Links • Digital Oscilloscope • Hard Disk Drive Read-Channel • Digital TV • Wireless Personal Area Network (WPAN) • Software Defined Radio

10. High speed ADC applications

11. ADC topologies • Flash • Pipeline • Successive Approximation Register (SAR) • Sub-ranging • Ramp • Single slope • Dual slope • Delta-Sigma

12. Flash ADC • N-bit flash: 2N -1 comparators • Vin connected with 2N -1 comparators in parallel • Comparators connected to resistor string

13. Flash ADC pros and cons • Pros • Very fast • Cons • Area and power increase exponentially with resolution • Input capacitive loading on Vin • Noise • Offset • Jitter sensitivity

14. Pipelined A/D converters • Widely used where high resolution and high throughput is required • A pipeline A/D converter is a multi-step amplitude quantizer • Cascade of stages of low-resolution analog-to-digital converters • Trades latency for speed

15. Pipeline A/D converters Coarse quantizer

16. Pipeline A/D converter Pros and Cons • Pros • High throughput • Easy upgrade to higher resolutions • Cons • Latency • High demands on speed and gain of amplifier(s) • High power

17. SAR ADC • Based on binary search • Consisted of a comparator, N-bit DAC, binary search logic • Compare VD/A with input signal Vin • Modify VD/A by D0D1D2…DN-1 until closest possible value to Vin is reached • Sequential converter Successive Approximation Register (SAR) ADC

18. 3-bit SAR ADC example

19. SAR ADC pros and cons • Pros • Small area • Low power • Cons • Low speed: N clock cycle for N-bit SAR ADC. • Complex clock generation at high sampling rates: • A 6 bit 300MS/s SAR ADC requires 2.1 GHz clock generator with low skew. • Clock generator consumes more power than the ADC itself!

20. Resolution vs sampling rate of ADCs • SAR ADCs are the most energy efficient ADC topologies but low speed • Can we design ADCs with efficiency of SAR and speed of flash converters.

21. Asynchronous SAR ADC • Problems with SAR • The logic delay in the feedback takes up to 75% of clock cycle • Complex clock generation • Solution: Asynchronous SAR/Binary Search ADC • No complex clock gen. • No binary search logic 4.5/8 0 0 1 1 1 ABS ADC 0

22. Asynchronous SAR ADC • Unroll feedback loop • N comparators are used. • Asynchronous clock is generated from MSB to LSB. • Speed is limited by N comparator delays and DAC delays

23. Asynchronous SAR pros and cons • Pros • Can operate faster than conventional SAR • No need for high speed clock generation • Cons • Offset between comparators • High resolution cannot be achieved like SAR because of the offset. • Larger area

24. Outline • Motivation and goals • Background • New ADC topologies proposed for high speed, low power and medium resolution • Asynchronous binary search ADC • Pipeline binary search ADC • Conclusion

25. Proposed ADC topologies • Asynchronous topologies • 2-bit/stage Asynchronous Binary Search (ABS) ADC • Hybrid topologies • Pipeline Binary Search (PBS) ADC

26. Proposed ADC topologies • Asynchronous topologies • 2-bit/stage Asynchronous Binary Search (ABS) ADC • Hybrid topologies • Pipeline Binary Search (PBS) ADC

27. 2-bit/stage ABS ADC • In a typical asynchronous SAR/binary search ADC speed is limited by N comparator, N DAC delays • How to speed up? • Resolve two bits in each stage (2-bit flash) • Speed limited by N/2 comparator delays and DAC delays. • Speed improvement by two times • Penalty • Power consumption increases by 1.5 times

28. 2-bit/stage ABS ADC Operation • Use a 2bit flash quantizer in each stage (3 comparators) • Break the reference into 4 intervals. • Combines sub-ranging and asynchronous processing ideas. • Break the flash ADC operation into multiple steps =9.5/16 =9.5/16 Asynch. CLK =9.5/16 =9.5/16 Asynch. CLK =9.5/16 =9.5/16 Asynch. CLK

29. 2-bit/stage ABS ADC implementation

30. 2-bit/stage ABS ADC simulation result

31. Proposed ADC topologies • Asynchronous topologies • 2-bit/stage Asynchronous Binary Search (ABS) ADC • Hybrid topologies • Pipeline Binary Search (PBS) ADC

32. Pipelined Binary Search ADC • How can we further speed up the binary search operation of Successive Approximation Register ADC? • Can we operate the Successive approximation algorithm in pipeline fashion? • By combining SAR and Pipeline architectures better performance than proposed ABS ADC were achieved. • Two new topologies of PBS are developed.

33. Pipeline Binary Search (PBS) ADC • SAR-ADC loop has to be unrolled. • Sampled input signal has to be delayed by an analog delay line. • N-comparators and (n-1) digital to analog converters (DACs) have to be used • Speed is limited to 1 comparator delay and DAC delays • How to delay an analog signal?

34. How to delay the analog signal? • Digital delay can be easily implemented using a D-latch or DFF • Analog delay line is implemented by interleaved sampling of the analog signal • Example: 2-clock cycle analog delay

35. 6 bit, PBS ADC Circuit Implementation • No opamp is used in this pipeline ADC • Lower power, higher speed

36. Layout for the PBS1 ADC DACs R-String Comparator Sample&Holds Clock ditribution

37. Simulation result for PBS1 ADC

38. Comparison with state of the art ADCs

39. Summary • High speed and low power analog to digital converters are essential part of many communication and signal processing applications • In this research new ADC topologies that take the advantage of energy efficiency of SAR ADCs while enabling high speed operation compared with conventional SAR ADCs architectures is proposed. • A new 2 bit/stage ABS ADC was introduced • Twice as fast as conventional ABS ADCs • A new ADC concept and implementation (PBS ADC) was introduced • Enables binary search operation in a pipelined fashion • Application of asynchronous ADCs as quantizers for high resolution ADCs

40. Thank you for your attentionQ&A