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Trigger Electronics for Upgrade LL1’s

Trigger Electronics for Upgrade LL1’s. Muon Trigger Upgrade Integration with existing MuID LL1 Use of Generic LL1 boards for tracking information NCC LL1 Trigger Channel count, density, LL1 data rates. 16-bit backplane bus. Muon Trigger Upgrade.

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Trigger Electronics for Upgrade LL1’s

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  1. Trigger Electronics for Upgrade LL1’s • Muon Trigger Upgrade • Integration with existing MuID LL1 • Use of Generic LL1 boards for tracking information • NCC LL1 Trigger • Channel count, density, LL1 data rates J. Lajoie - PHENIX Forward Upgrade Meeting

  2. 16-bit backplane bus Muon Trigger Upgrade • Need to combine MuID LL1 information with new trigger detectors (tracking). New Muon Trigger LVL1.5 VME crate N<20 fibers @ 6xBCLK 40 fibers @ 6xBCLK Existing MuID LL1 System J. Lajoie - PHENIX Forward Upgrade Meeting

  3. Muon Trigger Electronics • Combined Muon Trigger Needs MuID LL1 input • Use backplane databus to transfer MuID LL1 data to new muon trigger board • Can we use an existing GenLL1 trigger board? • Up to 20 fibers input data • Can the matching logic between MuID LL1 and the muon tracking chambers be put into one FPGA? • Detailed answers await decision on upgrade tracking chambers • Possible GenLL1 Rev2 • Revision of GenLL1 boards (not a redesign) • Revised terminations, double the available logic • Bring backplane databus into additional FPGA’s • Cost ~$35K • Don’t rule out using the vertex! • Requires revision of BBC LL1 • Not a large cost issue on the scale we are discussing • But does it help? J. Lajoie - PHENIX Forward Upgrade Meeting

  4. NCC LL1 Trigger • Lots of data at NCC LL1: • 10k channels over all three layers • 8 bits/channel @ 10Mhz = 800 Gbit/s • Factor of four lower if we use 2x2 sums (on FEMs) • This is between 5 and 20 times the current MuID LL1 (one arm) • Physical limitations make it unlikely we will get more than 20 fibers in a 9U board. • Absolutely critical we get all the data into one place as much as possible • Can’t send all of this to the counting house? • Consider using Gbit copper links over ~few meters to LL1 rack inside the IR • Use fiber to send the summary data to GL1 • Limited real estate! • How much FPGA logic do we need? • Need algorithm development, simulation J. Lajoie - PHENIX Forward Upgrade Meeting

  5. LL1 Time Budget • Current LL1 Latency ~15 clock ticks • Dominated by BBC LL1 (8 clock ticks) • MuID LL1 runs in 4 clock ticks • Some room to grow with sequential systems • Need to worry about data transfer between LL1 systems • Don’t want to push the 40-tick latency (some FEMs may break) J. Lajoie - PHENIX Forward Upgrade Meeting

  6. BACKUP SLIDES J. Lajoie - PHENIX Forward Upgrade Meeting

  7. Without square hole rejection: South 1 Deep rejection = 584.02 South 1 Deep 1 Shallow rejection = 28700.4 South 2 Deep rejection = 200903 North 1 Deep rejection = 376.929 North 1 Deep 1 Shallow rejection = 18263.9 North 2 Deep rejection = 66976.7 With square hole rejection: South 1 Deep rejection = 1014.66 South 1 Deep 1 Shallow rejection = 50225.8 South 2 Deep rejection = 200903 North 1 Deep rejection = 752.446 North 1 Deep 1 Shallow rejection = 50225.8 North 2 Deep rejection = 100452 MuID LL1 Rejection Study (pp) • Run MuID LL1 Hardware Simulator on BBCLL1 Events • Not enough clock triggers for unbiased study • All segments from Run 130553 (Run-4 pp, “clean” run) • 200903 BBC LL1 events • 3/5 gaps required for deep symset: ~2x better than the RF=250 that everyone is quoting…. (similar numbers from Kazuya’s talk yesterday) J. Lajoie - PHENIX Forward Upgrade Meeting

  8. The MuID Square Hole • MuID LL1 triggers dominated by hits close to square hole • Expected from background studies • Look at all horiz.,vert. combinations from symsets (all events) • Run-4 AuAu data: (square hole partly filled in by false combinations) J. Lajoie - PHENIX Forward Upgrade Meeting

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