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BPM Signal Processing

T. Straumann, M. Cecere, E. Medvedko, P. Krejcik SLAC B. Lill ANL. BPM Signal Processing. Requirements/Engineering Constraints Status Current Frontend Design Timeline for next 12 months. Overview for Stripline BPMs. Objective. High precision/resolution BPM Electronics

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BPM Signal Processing

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  1. T. Straumann, M. Cecere, E. Medvedko, P. Krejcik SLAC B. Lill ANL BPM Signal Processing

  2. Requirements/Engineering Constraints Status Current Frontend Design Timeline for next 12 months Overview for Stripline BPMs

  3. Objective • High precision/resolution BPM Electronics • 5um resolution (R ~ 12mm) • drift < 5um/h • low bunch charge: 0.2..1nC • Stripline sensitivity: V = (a-b)/(a+b) = 2 r / R • dynamic range > 60dB + 20dB

  4. Engineering Constraints • SNR expressed as position noise (LINAC Stripline; 150MHz) • dB[ r/1um ] = NF – dB[ q/1nC ] - ½ dB[ BW/1MHz ] 8dB > NF + 14dB(.2nC) – 10dB (10MHz) • noise figure including cable losses • stripline signal level based on estimation

  5. Mixer More signal at higher freq. Proven solution ADC performs better at IF LO generation + distribution New cables in LINAC needed Baseband vs. Mixer Baseband • Simpler • Cheaper • Use existing cables (?) • Only marginally meets resolution requirements

  6. System Overview Calibration scheme does not require extra cables Direct digitization

  7. Status • VME Digitizers + basic driver software available • Echotek • Joerger • SIS • New card ordered (13ENOB, 130MSPS, 700MHz input BW) • First frontend design + prototype (E. Medvedko) • Engineer hired (M. Cecere)

  8. Frontend • f0 =150MHz (enough signal, ADC still well performing) • Low noise, 10MHz BW • Low distortion • Alias suppression • Build Prototype • Test (noise, stability, out-of band performance, linearity) • Final Design • Interface (form factor, control signals, status monitors) • Calibration

  9. LNA ADC BPM Analog Front EndBaseband Design BPF#2 BPF#1 Signal from BPM or Hybrid Frequency Selection Filter Band Pass Filter Undersampling ADC Low Noise Amplifier Final Amplifier

  10. LNA ADC Baseband DesignComponent Selection Criteria BPF#2 BPF#1 Freq./BW determine SNR Low Insertion Loss Good OOB rejection Sharp Rolloff (Anti- alias) Flat Passband >= 119MSPS High Dynamic Range BW>= 200MHz Low NF Low Distortion Moderate Gain High Gain*BW Low Distortion @ High Output Level

  11. Timeline (Injector only)

  12. Calibration Bench Test • Measurement setup (not worse than required stability!!) • Test stability of calibration (splitters, BPM striplines) • Cross-talk issues? • Repeatability • Multiplexing (t/f) • Final design, integration

  13. LCLS Cavity BPM Overview • RF BPM system current status • Planning for prototype testing • Planning for 8 LTU BPMs electrically identical to those in the undulator. • Planning for 33 undulator BPMs

  14. Miteq X-Band Low Noise Receiver • Existing product line • WR 75 Waveguide Interface • Low Noise Figure (2.7 dB) • Prototype delivery date 12/10/05 • Budgetary price for prototype $6500.00 (for 3 channels)

  15. Prototype Receiver Specification

  16. Long Lead Item Status • Receiver Prototype del. 12/10/05 • Local oscillator del. 11/24/05 • Waveguide del. 12/1/05 • Waveguide calibration kit del. 12/9/05 • CPI Vacuum windows 11/30/05

  17. Phase I Injector Test Stand ITS Install single X-Band Cavity and modified off-the-shelf down converter receiver Mount BPM on Piezo two-axis translation stage Phase II Bypass line test with PC gun Install three X-Band Cavities BPMs Bypass line test with PC gun to start June 06 BPM System Test Approach

  18. Injector Test Stand ITS Beam Parameters • Charge- 1 nC single-bunch • Bunch length- ~ 3 - 4 ps FWHM for ps laser • Spot size on final screen at 5.5 MeV ~ 0.75 mm rms, ps laser

  19. Phase I Data Acquisition Design Approach • Instrument three channel down converters with Struck SIS-3301-105 ADCs 14-bit • Single VME board will provide the data acquisition for 8 channels • Epics driver complete • Digitize horizontal, vertical position and Intensity 0 to 1 volt range • Fit Data to decaying exponential at 60 MHz

  20. Phase I Testing Objectives • Test prototype Cavity BPM, down converter, and data acquisition • Generate preliminary compliance table to specification • Gain operational experience to determine if translation stage is useful, what are optimum operating parameters

  21. Phase I Schedule Milestones • Design and develop prototype Cavity BPM • Prototype non vacuum • Nov 05 • Build single Cavity BPM • Dec 05 • Cold Test • Dec 05 • Install cavity BPM into ITS and Test • Jan 06

  22. Phase II Schedule Milestones • Refine design and develop First Article Cavity BPM and support hardware • Jan 06 • Build 3 Cavity BPMs • Mar 06 • Cold Test • May 06 • Install cavity BPM into APS PAR/Booster bypass line and Test • June 06

  23. Phase II Testing Objectives • First Article Prototypes evaluated • Test three BPM separated by fixed TBD distance to determine single-shot • Complete test matrix

  24. LTU and Undulator Planning • Receiver and LO housed in shielded enclosure below girder 20 watt power dissipation maximum • Presently BPM output on wall side • BPM output flexible waveguide section allows movement for alignment

  25. BPM Mounting • BPM connects directly to the girder. • Mechanical translation stage used for alignment • BPM and Quad can be pre-aligned independently with respect to each other

  26. Undulator Planning

  27. Backup slides

  28. LNA ADC Baseband DesignComponents Alias image @ 30MHz BPF#2 BPF#1 Cable NF = 2-4dB NF = 3dB NF = 2-4dB LTC2208 130MSPSmax 16-bit 700MHz BW fsamp=119MHz Req. jitter < 350fs --------------------- AD6645 105MSPSmax 14-bit 200MHz BW fsamp=102? Req. jitter < 600fs fo= 150MHz BW = 10MHz Lark Engineering MS140-20-3CC Insert. Loss = 5.8dB -------------------------- TTE filters KB3T-150M-10M-50-3A Insert. loss = 4.1dB -------------------------- Microwave Filter Co. 3MB10-150/10-SF/SF-1 Insertion loss = 3dB TI OPA847 GBW = 3.9GHz Distortion -105dBc Sirenza SGA-6589 G = 26dB NF = 3.0dB OIP3 = 33dBm ------------------- Sirenza SGA-4363 G = 18dB NF = 3.1dB OIP3 = 29dBm Sawtek 854916 fo= 150MHz BW = 10MHz Insert. loss = 11dB

  29. Baseband DesignFrequency Response dBm Final output BPM signal Input signal Cable losses LNA BPF2 BPF1 Frequency MHz

  30. Mixer Based BPMBlock Diagram xN 43MHz 400-800MHz BPM ADC LNA RF IF or Hybrid LO 119MHz Minicircuits ZFM-2 1 – 1000 MHz Conv Loss = 5.8dB

  31. Mixer Based DesignFrequency Response dBm mixer BPM signal After coax LNA BPF1 BPF2 Frequency MHz

  32. Software Tasks • Evaluation / test software • BPM Processor • Processing algorithm • Real-time tasks: • data acquisition and processing • timing • history buffers • Calibration • Integration (SLC-aware IOC, timing, feedback) • Slow controls (gain, calib, status monitors, alarms)

  33. Integration; Hardware • Clock generation and distribution • Timing; triggers/gates • Calibration signal generation and distribution • Controls: gain, calib. mux • Power • Status monitors

  34. Integration; Software • Timing • SLC-aware layer • Shot-to-shot feedback • High-level applications (EPICS database) • Naming • Real-time • Sysadmin; infrastructure; network

  35. PDRO local oscillator • 11.424 GHz (119 MHz x 96) • Phase lock to 119 MHz ref 0 dBm +/- 3 dB • +13 dBm output power • In-Band Spurs <70 dBc • Phase noise depends on 119 MHz reference

  36. Noise Estimates • Sensitivity: -58 dBm/0.2nC/1m • Minimum bit size: 16 bits/micron@ 0.2nC • Assumes 2 gain ranges for 75 dB • Noise floor <200 nm rms

  37. APS Test Objectives • Develop a cavity BPM that meets system requirements and can be manufactured economically • Develop simulation model that correlates to prototype data • Transition from prototyping to production

  38. ITS Installation

  39. Cost Savings • Reduce the dipole cavity outputs from 4 ports to 2 ports • Terminate the unused ports in vacuum • Eliminate 2 transitions, 2 windows, waveguide, 2 magic tees • Prove resolution and offset performance

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