Mutiple Faults: Modeling, Simulation and Test

1. Mutiple Faults: Modeling, Simulation and Test Yong C. Kim University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA kimy@ece.wisc.edu Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA va@agere.com Kewal K. Saluja University of Wisconsin, Dept. of ECE, Madison, WI 53706, USA saluja@engr.wisc.edu Kim, et al., VLSI Design'02

2. Problem Statement • ATPG targets single stuck-at faults: • Efficient simulation and ATPG programs are available for single faults. • Some applications require a limited capability to selectively target multiple faults: • Combinational ATPG for partial scan; Kim, et al., VLSI Design’01, ITC’02. • Fault diagnosis. • Circuit optimization by redundancy removal. • Bridging faults. • Problem: To find a test for a multiple stuck-at fault using a single-fault ATPG procedure. Kim, et al., VLSI Design'02

3. Talk Outline • Background • A single fault model for multiple faults • Applications • Combinational ATPG for acyclic sequential circuits • Exclusive test for diagnosis • Conclusion • Other applications Kim, et al., VLSI Design'02

4. Background • Number of multiple stuck-at faults in a k line circuit is 3k-1. • Single-fault tests are found to cover most multiple faults: • Agarwal and Fung, IEEETC’81 • Hughes and McCluskey, ITC’86 • Jacob and Biswas, ITC’88 • Multiple-fault ATPG algorithms are not fault-oriented: • Bossen and Hong, IEEETC’71 • Kohavi and Kohavi, IEEETC’72 • Aboulhamid, et al., JETTA’93 Kim, et al., VLSI Design'02

5. An Obvious Fault Model s-a-1 New PI fixed at 0 • Fault is always active in the model even when it is not activated, e.g., a=1, b=0, c=0. • Some simulators and ATPG programs may not properly handle fixed logic signals. s-a-1 A a a A s-a-0 b B B b s-a-0 c C C c Kim, et al., VLSI Design'02

6. A New Single Fault Model • Insert a two-input in-line gate in each faulty line: • AND for s-a-0 fault • OR for s-a1 fault • Insert an AND gate with output s-a-1 fault s-a-1 s-a-1 A a a A s-a-0 b B B b s-a-0 c C C c Kim, et al., VLSI Design'02

7. Proof of Correctness • Fault-free circuit: • A = a + a b c = a • B = b ( a + b + c ) = b • C = c ( a + b + c ) = c A a a A b B B b c C C c Kim, et al., VLSI Design'02

8. Proof of Correctness • Faulty circuit: • A = a + 1 = 1 • B = b . 0 = 0 • C = c . 0 = 0 s-a-1 s-a-1 A a a A s-a-0 b B B b s-a-0 c C C c Kim, et al., VLSI Design'02

9. Size of Model • Model of a multiple fault of multiplicity n requires at most n+3 modeling gates. s-a-1 s-a-1 A a a A s-a-0 b B B b s-a-0 c C C c Kim, et al., VLSI Design'02

10. Comb. ATPG for Seq. Circuits • Single-fault tests for acyclic sequential circuits can be obtained by combinational ATPG. • Kim, et al., VLSIDesign’01, ITC’01. • A combinational model is made for the sequential circuit. • About 83% of sequential circuit faults map onto single faults in the combinational model. • On an average about 17% of sequential circuit faults map onto multiple faults in the combinational model. • The method allows 100% fault efficiency. • General sequential circuits can be made acyclic by partial scan; Cheng and Agrawal, IEEETC’90. Kim, et al., VLSI Design'02

11. An Example Unbalanced nodes a s-a-0 s-a-0 b FF dseq = 1 Combinational vector Balanced model Single fault 0 a1 s-a-0 s-a-0 0 1 X 1/0 b1 Multiple fault 1 a0 s-a-0 1/0 1/0 1 b0 FF replaced by buffer Test sequence: 11, 0X Kim, et al., VLSI Design'02

12. Acyclic Partial-Scan ISCAS’89 Circuits: Kim, et al., VLSI Design'02

13. Acyclic Partial-Scan ISCAS’89 Circuits: Test Generation FC: cov. (%), FE: efficiency (%), TGT: CPU s Sun Ultra 10 *Gentest for seq. and TetraMAX for comb. ATPG (Hitec produced equivalent FC, FE and TGT within 10% of Gentest) Kim, et al., VLSI Design'02

14. Exclusive Test • Given two faults, an exclusive test detects one fault but does not detect the other. • A test for the multiple fault (f1,f2) in the following circuit is an exclusive test for f1 and f2 in CUT. CUT with f1 Exclusive test vector 0/1 or 1/0 CUT with f2 Kim, et al., VLSI Design'02

15. Diagnostic Test Example Fault a1 b1 c0 c1 d1 f1 g0 h0 i0 i1 Test syndrome 10100 00010 00101 01010 00010 00100 00001 01000 01001 10110 Diagnostic number 5 8 20 10 8 4 16 2 18 13 a g d s-a-1 i s-a-1 b c h e f 100% coverage Tests: a 00011 b 01100 c 10101 Kim, et al., VLSI Design'02

16. Exclusive Test for b1 and d1 0 a g CUT with b1 d i 0 b 0 h c e f 0/1 s-a-1 g d i CUT with d1 h e f Kim, et al., VLSI Design'02

17. Diagnosis With Exclusive Test Fault a1 b1 c0 c1 d1 f1 g0 h0 i0 i1 Test syndrome 101000 000101 001010 010100 000100 001000 000010 010000 010010 101101 Diagnostic number 5 40 20 10 8 4 16 2 18 45 a g d s-a-1 i s-a-1 b c h e f 100% coverage tests and excl. test: a 000110 b 011000 c 101010 Kim, et al., VLSI Design'02

18. Conclusion • Single fault model allows effective use of existing single-fault ATPG and simulation tools to handle multiple fault. • Applications include: • Combinational ATPG for sequential circuits • Circuit optimization by removing multiple fault redundancies (see this paper) • Improving diagnostics by exclusive tests • Other types of tests like antitest and concurrent test (unpublished) • The modeling technique is useful for non-stuck type of faults that map onto multiple stuck-at faults, e.g., bridging faults (see this paper). Kim, et al., VLSI Design'02