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Test Station for the LHCb Muon Front-End Electronics

Software Architecture:. Hardware Schematic. Template. INJECTION BOARD. controlled parameters: injected charge threshold value channel to be injected frequency of injection time window to count injection polarity. Calibration. Crosstalk test. 74F38. channel. injection line.

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Test Station for the LHCb Muon Front-End Electronics

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  1. Software Architecture: Hardware Schematic Template INJECTION BOARD • controlled parameters: • injected charge • threshold value • channel to be injected • frequency of injection • time window to count • injection polarity Calibration Crosstalk test 74F38 channel injection line 16 channels charge value … Signal Conditioning Circuit Front End Electronics Board in test supply bus S-curve test Connectivity test Control Board CONTROLLING BOARD PCI-6025 FPGA front-end board channels 0 to 7 Injector Board counters Main Panel mux readout PC interface NI-DAQ enable channels 8 to 15 select reset Sensitivity test Rate Method test • NI-DAQ main features: • 2 DACs (12 bits) • 2 Counters (24 bits) • 3 8-bits I/O ports Test Station for the LHCb Muon Front-End Electronics * E. Polycarpo,G. Cernicchiaro, I. Bediaga, R. Nobrega, L. Manhaes de Andrade Filho, A Machado, J. Miranda, A. Reis, J. Magnin, F. Marujo, **B. Schmidt Centro Brasileiro de Pesquisas Físicas - CBPF, Brazil * Universidade Federal do Rio de Janeiro - UFRJ, Brazil ** CERN Introduction Front End Electronics Test – FEET System The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions • Tested Parameters: • Connectivity • Power consumption • Sensitivity and offset • Noise • Time response and width Laboratory infrastructure System Separate ground lines for computers and power supplies, temperature control, workbenches with ESD protection equipment, grounded cupboard to store the chips. Results Conclusion Identification of the fraction of failed chips (dead channels): CARIOCA: (11±1)% CARIOCA GEM: (10%) Failure rate due to connectivity or offset deviations: CARIOCA:(6±1)% (with offset<10% and sensitivity<17.5%) CARIOCA GEM : (6±3)% (with offset<10% and sensitivity<10.0%) The characterization rate is around 100 chips/day (1 station) The rate can be improved by robotization and by optimization of the parameters for test, instead of characterization Overall Sensitivity Current Consumption Overall Noise • Carioca Correlation Cut

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