Monday March 10 , 2014 Interrupts, Cont’d Review for Midterm Continue Lab4

Monday March 10, 2014 • Interrupts, Cont’d • Review for Midterm • Continue Lab4

Interrupts

Von Neumann MSP430 Architecture Instructions and Data Input / Output Processing Unit (CPU)

MSP430 Architecture I/O

MSP430F5438A Architecture Let’s take a closer look… Mostly just adding more peripherals with each generation. CPU doesn’t change much.

Can I use a port to interrupt my program? Yes! How…?

Maybe the User Guide is a good place to start… I count three “and” qualifiers. Let’s take Them one at a time, in reverse order… …and by the way, what’s that?

What has to happen for an interrupt to occur. 1. An interrupt has to be requested by the peripheral (IRQ). 2. The peripheral interrupt enable (PIE) bit must be set. 3. The General Interrupt Enable (GEI) bit must be set. 4. An Interrupt Service Routine (ISR) has to be run.

Let’s tackle the hard part first: 1. An interrupt has to be requested by the peripheral. 2. The peripheral interrupt enable (PIE) bit must be set. 3. The General Interrupt Enable (GEI) bit must be set. 4. An Interrupt Service Routine (ISR) has to be run. An ISR is a subroutine pointed to by the Interrupt Vector.

Interrupt Vectors Each peripheral device is assigned an address. It is device dependent, hard-wired, not changeable. A vector is basically a pointer: It points to an address.

First, find it’s interrupt vector address. 0xFFD4 This memory location is very special (if you’re Port2): It is assigned to Port2 forever. How do I know this…

So which interrupt vector is mine? Look at the Interrupt Vector Address Table: Scrolling thru the table…

Practical Consideration: How does CCS know this? My_ISR: <code> RETI Linker cmd file: MEMORY INT42 : origin = 0xFFD4, length = 0x0002 SECTION PORT2 : { * ( .int42 ) } > INT42 type = VECT_INIT Label must match <code> .sect “.int42” .short My_ISR

Let’s go back to the peripheral slide 0x5c2c: My_ISR 0x5c2e: <code> 0x5c2c 0xFFD4 This memory location is very special (if you’re Port2): It is assigned to Port2 forever.

Step 1: Set the GIE General Interrupt Enable must be set for any maskable interrupt to be serviced. Three ways to do it: bis.w #0x04,SR OR… eint OR bis.w #GIE,SR They alldo the same thing

OK, GIE set, what next? Let’s look at the Peripheral IE (PIE) next… Check!

Now that I’ve set the GIE, it looks like I need to get peripheral-specific. TI calls them modules. OK, so which module am I…?

Looking further down the User Guide… Device Specific? That’s not very helpful!

Let’s look at the Digital I/O Section in the User’s Guide: Getting closer…!

Step 1: Set the GIE Step 2: Set the PxIE Peripheral Interrupt Enable must also be set for any maskable interrupt to be serviced. Example: Set P2.6 IE: Two ways to do it: bis.w #0x40,&P2IE OR… bis.w #BIT6,&P2IE They both do the same thing

OK, GIE and PIE set, what next? PIE Check! GIE Check! eint ;GIE set bis.w #BIT6,&P2IE ;P2.6 IE set

Interrupt Request

What has to happen for an interrupt to occur. 1. An interrupt has to be requested by the peripheral (IRQ). 2. The peripheral interrupt enable (PIE) bit must be set. 3. The General Interrupt Enable (GEI) bit must be set. 4. An Interrupt Service Routine (ISR) has to be run. First.asm

Interrupts Processing an Interrupt… • Processor completes execution of current instruction. • Master Clock (MCLK) started (if CPU was off). • Processor pushes Program Counter (PC) on stack. • Processor pushes Status Register (SR) on stack. • Interrupt w/highest priority is selected. • Interrupt request flag cleared (if single sourced). • Status Register is cleared: • Disables further maskable interrupts (GIE cleared) • Terminates low-power mode • Processor fetches interrupt vector and stores it in the program counter. • User ISR must do the rest!

Interrupt Vector Table 0xFFC0 0xFFBF Program Code 0xC000 0xBFFF 0x0400 0x03FF Stack 0x0200 0x01FF Input/Output Interrupts Interrupt Vectors 0xFFFF • The CPU must know where to fetch the next instruction following an interrupt. • The address of an ISR is defined in an interrupt vector. • The MSP430 uses vectored interrupts where each ISR has its own vector stored in a vector table located at the end of program memory. • Note: The vector table is at a fixed location (defined by the processor data sheet), but the ISRs can be located anywhere in memory. 16 vectors (ISR Addresses) 0x0000

Interrupt Process Interrupt Flag Ie, save Activation Record to Stack

Interrupts Interrupt Flags • Each interrupt has a flag that is raised (set) when the interrupt is pending. • Each interrupt flag has a corresponding enable bit – setting this bit allows a hardware module to request an interrupt. • Most interrupts are maskable, which means they can only interrupt if 1) Individually enabled and 2) general interrupt enable (GIE) bit is set in the status register (SR). • Reset and Non-Maskable Interrupts (NMI) are reserved for system interrupts such as power-up (PUC), external reset, oscillator fault, illegal flash access, watchdog, and illegal instruction fetch. Device Interrupt Interrupt Enable Interrupt MPU General Interrupt Enable (GIE) Reset / Non-Maskable (NMI)

Interrupts MSP430 Interrupt Vectors Non-Maskable Interrupts Timers Ports

Prior to Interrupt Item 1 SP SP SP Item 2 • Interrupt (hardware) • Program Counter pushed on stack • Status Register pushed on stack • Interrupt vector moved to PC • Further interrupts disabled • Interrupt flag cleared Item 1 Item 1 Item 2 Item 2 PC PC SR SR • Return from Interrupt (reti) • Status Register popped from stack • Program Counter popped from stack Interrupts Interrupt Stack add.w r4,r7 jncmain add.w #1,r6 add.w r5,r6 add.w r4,r7 jncmain add.w #1,r6 add.w r5,r6 PC PC PC Execute Interrupt Service Routine (ISR) xor.b #1,&P1OUT reti

Reset Vector Another way to figure out how to use interrupt vectors…just look at the one that’s already in use by default in CCS when you start an assembly-only project: ;------------------------------------------------------------------------------- RESETmov.w #__STACK_END,SP ; Initialize stackpointer ;------------------------------------------------------------------------------- ; Main loop here ;------------------------------------------------------------------------------- ;------------------------------------------------------------------------------- ; Interrupt Vectors ;------------------------------------------------------------------------------- .sect ".reset" ; MSP430 RESET Vector .short RESET

Return From Interrupt Single operand instructions: Emulated instructions: Interrupt Service Routine

Interrupt Service Routine Interrupt Latency • The time between the interrupt request and the start of the ISR is called latency • MSP430 requires 6 clock cycles before the ISR begins executing • An ISR may be interrupted if interrupts are enabled in the ISR • Well-written ISRs: • Should be short and fast – get in and get out • Require a balance between doing very little – thereby leaving the background code with lots of processing – and doing a lot and leaving the background code with nothing to do • Applications that use interrupts should: • Disable interrupts as little as possible • Respond to interrupts as quickly as possible

Multi-Source Interrupt Handlers 1 Vector Address 8 Interrupt Flags

Multi-Source Interrupt Handlers IRQ[7:0] 8-bit bus shared by Port2 Interrupt Vector

Multi-Source Interrupt Handlers Solution: poll the interrupt flags to determine which port issued the interrupt. For example: port2_ISR: bit.b #BIT6,&P2IFG ; S1 Interrupt? jz end ; if not, exit

Monday March 10 , 2014 Interrupts, Cont’d Review for Midterm Continue Lab4