1 / 18

people involved in SOIPIX: G.Deptuch , S.Holm , F.Khalid , R.Lipton , A.Shenai , M.Trimpl

SOI pixel detector technology US-Japan collaboration Farah Khalid on behalf of ASIC Development Group SOIPIX collaboration. people involved in SOIPIX: G.Deptuch , S.Holm , F.Khalid , R.Lipton , A.Shenai , M.Trimpl. Target for work at Fermilab :.

binah
Download Presentation

people involved in SOIPIX: G.Deptuch , S.Holm , F.Khalid , R.Lipton , A.Shenai , M.Trimpl

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. SOI pixel detector technology US-Japan collaborationFarah Khalidon behalf of ASIC Development GroupSOIPIX collaboration people involved in SOIPIX:G.Deptuch, S.Holm, F.Khalid, R.Lipton, A.Shenai, M.Trimpl

  2. Target for work at Fermilab: • SOI Active Pixel Sensors (SOIAPS)work is one of Fermilabdetector R&D directions • Fully exploit advantages of the SOI technology for integrated circuits combined with a sensor monolithically • It is a great opportunity to develop solutions together with KEK and LAPIS Semiconductor (former OKI Semiconductor) Yasuo Arai Fermilab SOIPIX Collaboration

  3. SOIPIX: collaborative efforts seen from Fermilab • Outstanding value of the SOIPIX collaboration is trusted and direct relation with the technology vendor • Technology is based on commercial, voluminous 0.2mm CMOS process, which is indispensable for the electronics operating properly and having predictable and repetitive performance • Exploration of SOI for pixel detectors • Maturing of the technology, visible through significant extensions and modifications included into the original process, may eventually lead to a transition from pure research to use for specific applications Fermilab SOIPIX Collaboration

  4. Fermilab’s SOI R&D with OKI process at Fermilab: 7 prototype, pixel detectors have been submited over last 5 years, Mainstream: MAMBO : Monolithic Active Matrix with Binary Counters, and Research on alternative detector biasing • MAMBOs: Monolithic Active Pixel Sensors with Binary Counters • 2006 MAMBOI 2.5×2.5 mm2, • 2008 MAMBOII 5×5 mm2, • 2010 MAMBO III (3D) 2×5×5 mm2 and MAMBO IV 5×5 mm2, • 2011 MAMBO V 6x6 mm2 • resistive baising test structure 2.5×2.5 mm2, • OKI drift imager ASIC (2011 ) 3x6 mm2

  5. Major Fermilab Contribution: Nested Well structure Implemented collaboratively and successfully by LAPIS (OKI) in the SOI process NestedBNW/BPW BPW • - electric potential under any circuitry may be kept constant or change very little only by voltage from integrated charge • gives increased C-to-V node capacitance • works with charge integrating pixels (3T-like), gain may be nonlinear, • charge injections due to electronics activity may be cancel out by sequential readout with exactly repeated patterns for control signals and CDS • full isolation of the electronics and the detector charge collection node, • electric potential under any circuitry is kept constant (AC ground) • allows designs with amplification stages and virtual ground (CSA) • Removes parasitics feedbacks and instabilities, • Unfortunately increases input capacitance of CSA

  6. Purpose of the nested well structure Shielding: • Tripple role of shielding between the SOI electronics and detector layer: • to avoid back-gating in transistors (DC potential underneath the BOX shifts threshold of transistors), • to avoid injection of parasitic charges from the SOI electronics to detector, • to avoid strong electric field in BOX that results in accelerated radiation damage. This well collects the charge carriers This well separates digital circuits from sensor substrate and prevents back gating effects SILVACO process simulatiom Fermilab SOIPIX Collaboration

  7. Example of MAMBO IV results: no shift of NMOS transistor IDS/VGSin nested wells at back-gate biases ranging from 0 to full depletion Results from MAMBO IV Multi-year program at Fermilab: Explored HR FZ 7.1 kΩcm material and appeciated improved PDK and models 2 BNW Voltages used for illustration Full depletion • FZ 7.1 kΩcm ~485 mm Fermilab SOIPIX Collaboration

  8. Details of MAMBO designs MAMBO III, IV & V pixel design with window discriminator and per pixel counter integrating CSA w/ pole-zero network, shaping filter CR-RC2with tp=200ns; gain=~100 mV/e-, ripple counter reconfigurable into shift register, DACs for threshold adjustment, control logic for testability Fermilab SOIPIX Collaboration

  9. MAMBO III: vehicle for exploring m-bump-bonding with T-micro MAMBO III : Top chip: Electronics single pixel (100µ x 100µ); ~950 transistors • 5x5mm2, 44x44 pixel matrix • T-Micro: 3D Au-In µ-bump bonding – only one 3D chip received in March 2012, process seems to be maturing • Bottom chip: matrix of detector pixels, no bond pads contains only micro bump pads, aligned with the top chip top chip: Pads with back metal opening Fermilab SOIPIX Collaboration

  10. SOI and 3D: (received March 2012) MAMBO III: 3D-bonded device, view from back-thinned side of electronics Back-side deposited shielding metal TOP: Electronics BOTTOM: sensor Aligned bonding targets pads Fermilab SOIPIX Collaboration

  11. Tests of MAMBO and other SOI device… National Instruments based tests setup - bought using US-Japan funds (ASIC tests WH14W) Fermilab SOIPIX Collaboration

  12. Tests of MAMBO V Progress of tests: • Tests of MAMBO V are progressing • Major components of the signal processing chain are functional performed threshold scan of discriminators all 2600 pixels respond!(base-line restorer, trimming DAC, discriminators) • First radiation events counting pixel device in SOI that is operational DAC values varied from 0000 to 1111; Comparator changing state from 0 – 1 as the current in the comparator is steered between the two branches Fermilab SOIPIX Collaboration

  13. MAMBO V: Electronics (Received Feb 2012) First Image using 1mmTungsten Mask, 22kEv source Without depleting the detector mask

  14. Resistive biasing imager and past results concept of resistive biasing Fe55-Image obtained with 2009 submission (based on Cz) • experienced high leakage current through bulk • No resistive biasing 20um pixels - diode still p-in-n (e.g. here) - moderate voltage (around 10V) applied to backside - additional n-in-n rings biased to create drift field - collection time of 100ns in 250um detector: 10-15V on backside sufficient - n-ring(s) at front side create(s) additional lateral drift field to improve charge collection 40um pixels random ghost hits Marcel Trimpl, Fermilab

  15. New submission / New test setup - Improved setup with dedicated PCB with fast analog buffers for 25MHz operation - cooling setup down to -40C (reduce/study leakage) new submission on Oct2011 run (6x3mm area) Diode with BPW (20x20um pixel – 1 drift ring) - improved pixel circuitry - improved row/column operation -> to enable 25MHz pixel rate Diode with BPW (40x40um pixel – 2 drift rings) - chip recently wire bonded to PCB - tests on basic operation of chip & RO chain in near future - waiting for chips with Fz substrate for more detailed studies Marcel Trimpl, Fermilab

  16. Some thoughts about forging SOIPIX… • Some thoughts about growing detector R&D program now: • The scientific contents of the SOIPIX activities is great, but to succeed we need to select and target applications that would exploit the advantages of the technology • Resources, at Fermilab, are limited and currently generic R&D projects, like SOI pixels, may experience difficulties in prioritization • Expected budgets are tight (real risk of ceasing some activities) • Some thought on possible way of proceeding: • Attempt sharing resources: design pieces and manpower • Select some designs, e.g. X-ray imager or charged particle tracker, build specification and distribute design amongst participating institutions (one leader per design) • Build and maintain library of blocks • Perfecting device models (we experience severe convergence problems) • Solving problem pertaining to parasitic extraction Fermilab SOIPIX Collaboration

  17. SOIPIX: Conclusions • Significant developments have been made including: • implementation of BPW • nested BNW and BPW developed jointly with Fermilab for effective shielding • enlargement of the reticle dimensions together with stitching of reticles for larger sensors and • thinning and back-side processing. • Among several applications which are of interest, large-surface detectors for soft X-ray (counting events or performing other dedicated functions, such as time of arrival) and detectors for tracking in HEP (but TID!) are particularly appealing • Inter-institutional collaboration can be very efficient in these topical developments Fermilab SOIPIX Collaboration

  18. Thank you Fermilab Institutional Review, June 6-9, 2011

More Related