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KM3NeT CLBv2

KM3NeT CLBv2. First ping!. Thanks to Vincent:. UDP Packet Transmit/Receive LM32_2 nd ipmux interface. 31 TDCs. IP/UDP Packet Buffer Stream Selector (IPMUX). Start Time Slice UTC & Offset counter since. Fifo. TDC0. Time Slice Start. RxPort 1. RxPacket Buffer 64KB. 31 PMTs.

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KM3NeT CLBv2

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  1. KM3NeT CLBv2

  2. First ping! • Thanks to Vincent:

  3. UDP Packet Transmit/Receive LM32_2ndipmux interface 31 TDCs IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Fifo TDC 30 Rx Stream Select Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S aux_master State Machine Management & Config. 6 1 7 Pause Frame 5 ADC 0 Fifo 4 Hydrophone 2 3 Alldone! TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx Stream Select Tx_pkt2mac Tx_pkt2mac Tx_data2buf Multiboot 0 1 Flags 2 TxPort_m S Management & Control Nano Beacon S ext_wb M M M M S M M M M M Debug LEDs WB Crossbar (1x8) WB Crossbar (2x3) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C SPI UART Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  4. Status 31 TDCs IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Fifo TDC 30 Rx Stream Select Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_src wrf_snk Flags RxPort_m Management & Control S aux_master State Machine Management & Config. 6 1 7 Pause Frame 5 ADC 0 Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx Stream Select Tx_pkt2mac Tx_pkt2mac Tx_data2buf Multiboot 0 1 Flags 2 TxPort_m S Management & Control Nano Beacon S ext_wb M M M M S M M M M M Debug LEDs WB Crossbar (1x8) WB Crossbar (2x3) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  5. Vincents slow-control temperature readout • Networking works! • Slow control interface now over fiber (Ethernet, UDP, SRP & MCF) • MAC & temperature are loaded from WRPC and displayed • IP address currently fixed (192.168.1.10) -> bootp / DHCP? • New architecture broke CLB_Bridge functionality, 1Gbps fiber works, but UDP over UART not -> when fixed, SVN commit, probably this week

  6. Vincents slow-control temperature readout exercises a lot of functionality! 31 TDCs IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Fifo TDC 30 Rx Stream Select Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S aux_master State Machine Management & Config. 6 1 7 Pause Frame 5 ADC 0 Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx Stream Select Tx_pkt2mac Tx_pkt2mac Tx_data2buf Multiboot M1 Flags M0 TxPort_m S0 S S1 Management & Control M2 S2 S M M M M Debug LEDs S M M M GPIO M M S M WB Crossbar (1x8) WB Crossbar (3x3) WB Crossbar (3x3) S S S S2 S S M M1 M2 I2C3 SPI UART 2nd CPU LM32 I2C1 I2C2 Xilinx Kintex-7 S0 MEM S M0 S1 M Data UTC time & Clock (PPS, 125 MHz) Debug RS232 Temp Nano Beacon Tilt & Compass SPI Flash Control Point to Point interconnection Wishbone bus

  7. PAUSE frames • TX Pause implemented • request the shore station to halt • RX Pause NOT implemented (yet) in white rabbit firmware • Respond to shore station halt request

  8. SVN Organization • One CLBv2 Design • Different implementations, that is: • VHDL top file • Synthesis KC705 / CLBv2 Proto Different UCF files!

  9. Testing CLBv2 proto • Looking forward to receive a CLBv2 prototype that is electrically tested and firmware loadable. • Don’t forget to ship one power board! • I’ll port the current KC705 design to the CLBv2 prototype (i.e. another place & route with the CLBv2 proto ucf file prepared by Antonio. • Exercise the board (implicitly testing a lot of the functionality)

  10. CalibrationLink delay model • dms, dsm: known fiber delays • (can be measured by solving timestamp measurements of fiber1, fiber2 and fiber1+2 • es, em: bitslide values • known by software • Dtx, Drx: unknown… • Hardware specific calibration parameters • a: Asymetry factor • fiber specific parameter

  11. Calibration • KC705 Dtx and Drx measured. • Not a precise measurement yet, just to know if we understand the principles… • Measure by feeding the tx/rx timestamp signal via register in IOLOGIC to pin (i.e. known delays and not depending on different synthesis cycles) • And comparing this with Ethernet packet SOF in the serial bit stream at the electrical entry of the SFP • Next: see if these numbers are okay; that is do they give a proper PPS alignment for setups: • KC705 <-> KC705 • KC705 <-> SPEC • Measure SPF propagation delays (Henk Peek)

  12. Status Listing • Skip the “done” list. Is’t getting long! • Currently: • Calibration procedure • To do list (in order of priority): • Study: Every now and then16 ns phase jump after startup • Study: Fucntionsdb_find_devices fails (dev/sdb.c). Under investigation… • Study: Reset button on the KC705 puts the system in a weird state • Implement Rx Pause frames (if the white rabbit guys aren’t fixing this already in the next WRPC release) • Wish list: • LM32 debugger

  13. Backup SlidesMore details…

  14. LM32_2ndipmuxCPU-FIFO interface 1 LM32_2nd transmits a packet 2 LM32_2nd receives a packet

  15. Transmit PAUSE frames IPMUX Rx Buffer of 64 KB can hold 7 complete Jumbo Frames (9000 bytes + MAC_Hdr{6 + 6 + 2} = 9014 bytes) When “High Water Mark” is reached (i.e. buffer fills up after reception of 4 Jumbo Frames), then a Pause Request (0xFFFF) is issued. When “Low Water Mark” is reached (i.e. buffer empties and there is still 1 Jumbo Frame available), then a Pause Request (0x0000) is issued which means “Cancel the Pause Request” Low Water Mark (@ 30 %) High Water Mark (@ 50 %)

  16. Transmit PAUSE framesSmall bug in ep_tx_framer.vhd globally assigned 48-bit multicast address 01:80:C2:00:00:01 case counter(3 downto 0) is when x"0" => q_data <= x"0180"; when x"1" => q_data <= x"c200"; when x"2" => q_data <= x"0001"; when x"3" => q_data <= regs_i.mach_o; when x"4" => q_data <= regs_i.macl_o(31 downto 16); when x"5" => q_data <= regs_i.macl_o(15 downto 0); when x"6" => q_data <= x"8808"; when x"7" => q_data <= x"0001"; when x"8" => q_data <= tx_pause_delay; state <= TXF_PAD; when others => null; “our” MAC address MAC Control code 0x8808 Added missing MAC Control opcode (0x0001) forsending a PAUSE frame. See IEEE 802.3 Table 31A-1 MAC control codes PAUSE (Annex 31B) PAUSE Quanta

  17. Transmit PAUSE frames • Hold IMPUX Rx buffer readout while sending Jumbo Frames from PC to KC705 Evaluation kit • (GPIO_DIP_SW => SW11-1 implements readout enable) send 4 Jumbo frames (4x ./ipsar txdata0.ips jumbo.bin) KC705 responds with Pause Request 65535 Enable Readout (SW11-1) = Empty RX buffer => KC705 sends Pause Request 0 Again send 4 Jumbo frames Again Pause Request 65535

  18. Receive PAUSE frames(ep_rx_path.vhd) • Signals “ematch_is_pause” and “ematch_pause_quanta” are implemented but “open” xwrf_mux (= Fabricredirector) 1 0 2 3 4 5 7 8 9 1 6 fab_pipe IPMUX ep_rx_early_address_match ep_rx_status_reg_insert ep_rx_buffer ep_packet_filter ep_clock_alignment_fifo ep_rx_oob_insert ep_rx_crc_size_check ep_rx_vlan_unit ep_rtu_header_extract ep_rx_wb_master 0 xwr_mini_nic

  19. LM32_2nd integrationtwo way bridge • LM32_2nd is able to access LM32_wrpc memory space at addresses 0x00100000-0x00130000 • LM32_wrpc is able to access LM32_2nd memory space at addresses 0x00100000-0x00140000 • Fucntionsdb_find_devices fails (dev/sdb.c). Under investigation… 0x00140000 SDB 0x00130000 SDB 0x00130000 SDB MEM 0x00120800 SDB S IO IO Master Master 0x00120000 0x00120000 M MEM MEM 0x00100000 0x00100000 LM32 WRPC M M1 S0 M0 S1 S2 M2 0x00040000 SDB 0x00030000 SDB 0x00030000 SDB 0x00020800 SDB Slave Slave IO IO WB Crossbar (3x3) WB Crossbar (3x3) 0x00020000 M M1 M2 0x00020000 LM32 2nd S0 MEM S2 S M0 S1 MEM MEM M 0x00000000 0x00000000

  20. CalibrationSimulated timing txts_odebug pin on FPGA sfp_tx_i: Tx SFD <D21.6> PCS-Tx SFD <0x55D5> sfp_rx_i: Rx SFD <D21.6> PCS-Rx SFD <0x55D5> rxts_odebug pin on FPGA sfp_txp_i -> txts_o Pin to pin delay: 46.845 ns Tx timestamp counter -> txts_o = 0 ns Rx timestamp counter -> rxts_o = 0 ns sfp_rxp_i -> rxts_o Pin to pin delay: = 494,140 ns (Note: bitslide = 0x0D = 13x800 ps = 10.4 ns)

  21. Examplemeasured: sfp_tx_p/n_orelativetotxts_o txts_o FMC XM105 J1 pin5 sfp_tx_p/n_o (SFP Connector pin 18,19) 57.80 ns 0010010111 K27.7 /S/ 1100000101 K28.5 0101011010 D21.2 0x55 0101011010 D21.2 0x55 0110111010 D16.2 0101011010 D21.2 0x55 0101011010 D21.2 0x55 0101011001 D21.6 0xd5 0101011010 D21.2 0x55 0101011010 D21.2 0x55

  22. Dtx, Drxmeasured • Dtx • (diff_probesft_txsignaltotxst_o) – (probe offset) – (txts_opropagation delay) • = 57.80 - 2.21 - 3.82 = 51.77 ns • simulation (no PCB routing and buffer delays) = 46.85 ns • Differs = 4.92 ns frommeasuredvalue • Drx • “(diff_probesft_rxsignaltorxst_o) – (probe offset) – (rxts_opropagation delay) – (bitslidevalue x 800 ps) • = 497.97 - 2.21 - 3.82 – 4.0= 487.94 ns • simulation(no PCB routing and buffer delays) = 494,14 ns • Differs6.2 ns frommeasuredvalue

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