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5.8GHz CMOS 射頻前端接收電路 晶片設計實作 5.8GHz CMOS Front-End Circuit Design

5.8GHz CMOS 射頻前端接收電路 晶片設計實作 5.8GHz CMOS Front-End Circuit Design. Process: U18-95A FTP No.: 42 Date: 2005/02/06. Outline. Introduction & Motivation Architecture & Schematic Simulated Results Layout Specification Table Measured Considerations References. Introduction & Motivation.

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5.8GHz CMOS 射頻前端接收電路 晶片設計實作 5.8GHz CMOS Front-End Circuit Design

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  1. 5.8GHz CMOS 射頻前端接收電路晶片設計實作5.8GHz CMOS Front-End Circuit Design Process: U18-95A FTP No.: 42 Date: 2005/02/06

  2. Outline • Introduction & Motivation • Architecture & Schematic • Simulated Results • Layout • Specification Table • Measured Considerations • References

  3. Introduction & Motivation 人們對於無線通訊的資料量需求越來越 高，在CMOS技術已經越來越成熟的情況 下，低成本、低電壓、高整合度的優點 下，來實現射頻前端接收電路實作，並藉 著特殊架構來取代電感在晶片中的使用面 積。

  4. Architecture & Schematic A block-level diagram of a 5.8GHz Front-End

  5. Schematic (LNA & Balun) LNA Passive Balun

  6. Schematic (Mixer & Active Inductor) Active Inductor Mixer Gilbert cell Mixer

  7. Schematic (Single-end Output Amplifier)

  8. Simulated Results (LNA) Noise Figure S-Parameter

  9. Simulated Results (LNA) P1dB Input P1dB=-26.5 dBm Output P1dB= -9.69dBm OIP3 OIP3=-2.46dBm (RF=-80dBm)

  10. Simulated Results (Balun) v2 v1 v3

  11. Simulated Results (Active Inductor)

  12. Simulated Results (Mixer) Conversion Gain S-Parameter S(1,1) => RF Port S(3,3) => IF Port

  13. Simulated Results (Mixer) P1dB Input P1dB= -31.9 dBm Output P1dB= -0.61 dBm RF=-70 dBm LO= -5 dBm NF=15.38 dB

  14. Simulated Results(1) S-Parameter Gain

  15. Simulated Results(2) P1dB Input P1dB=-41.1dBm Output P1dB= 1.05dBm Noise Figure= 6.89dB

  16. Post layout simulation S-Parameter

  17. Layout Active Inductor Mixer Gnd Vbias Gnd VDD & Vbias Vbias Gnd Balun Vbias LO- Gnd Vifout Single- Ended output VDD Vbias Gnd Gnd Vbias Vbias Vbias Gnd Vbias LNA LO+ Vbias Gnd Vbias Gnd Gnd Gnd VDD & Vbias Chip size 1.385mmX2.265mm Gnd Vbias RFin

  18. Specification Table

  19. Measured Considerations 1. 量測方式採用打磅線 on board的方式，並且已將磅線及外 部效應考量進去。 2. 量測儀器 HP 8722ES： 40GHz Network Analyzer HP 85047 ： 6GHz S-Parameter test set HP 8651 ： 6GHz Spectrum Analyzer HP 8970B ： Noise Figure Meter Agilent E8247C：20GHz PSG CW Signal Generator

  20. Reference [1] B. Gilbert, “The MICROMIXER: A highly linear variant of the Gilbert Mixer using a bisymmetric Class-AB input stage”, IEEE J. Solid-state Circuit, vol. 32, pp.1412-1423, Sept. 1997. [2] Behzad Razavi, “A 5.2-GHz CMOS Receiver with 62-dB Image REjection”, IEEE J. Solid-state Circuit, vol. 36, No. 5, pp.810-815, May. 2001. [3] Behzad Razavi, “A 2.4-GHz CMOS Transceiver for Bluetooth ”, IEEE J. Solid-state Circuit, vol. 36, No. 12, pp.2016-2024, DEC. 2001. [4] Zhenbiao Li, “A Dual-Band CMOS Front-End With Two Gain Modes for Wireless LAN Application”, IEEE J. Solid-state Circuit, vol. 39, No. 11, pp.2069-2073, Nov. 2004. [5] Xuezhen Wang, Robert Weber, and Degang Chen, “A NOVEL 1.5V CMFB DOWN CONVERSION MIXER DESIGN FOR IEEE 802.11A WLAN SYSTEM”, Iowa State University Press, 2004.

  21. Reference [6] Behzad Razavi, “RF Microelectronics”, Prentice Hall PTR,1998. [7] Thomas H. Lee. “The Design of CMOS Radio-Frequency Integrated Circuit”, Cambridge University Press, 1998.

  22. 謝謝各位評審老師指導

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