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Máquinas de Estados Finitos (MEF) Finite State Machines (FSM). MEF convencionais. X 1. Circuito Combinatório. Y 1. X L. Y N. D R. D 1. T 1. T R. Memória ( R-bit register ). clock. reset. Exemplo :.
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Máquinas de Estados Finitos (MEF) Finite State Machines (FSM)
MEF convencionais X1 Circuito Combinatório Y1 XL YN DR D1 T1 TR Memória (R-bit register) clock reset
Exemplo: Para um dado vector binário BVector de N bits verificar se este vector contém M uns consecutivos: responder Sim (Yes) ou Não (No) Exemplo: BVector = 0101011011101011; N = 16; dado M = 3 resposta é Yes dado M = 2 resposta é Yes dado M = 4 resposta é No O próximo slide mostra o grafo de MEF
BVector(Index) = 1 - X1 BVector(Index) = 0 - not X1 count=M - X2 countM - not x2 Index=N-1 - X3 Index N-1 - not X3 countM and IndexN and BVector(Index) = 1 a3 count=M Count ++ Index ++ Result: Yes countM and Index=N y1: Count=0; y2: Index=0; y3: Count++; y4: Index++; y5=1: Yes y5=0: No BVector(Index) = 1 a1 a4 a0 Result: No Count = 0 Index = 0 countMandIndexN and BVector(Index) = 0 BVector(Index) = 0 a2 Index=N Index ++ Count=0 reset = 1 A={ao,…,a4}; X={X1,X2,X3}; Y={y1,…,y5}. BVector(Index) = 1 and Index N BVector(Index) = 0 and Index N
y1: Count=0; y2: Index=0; y3: Count++; y4: Index++; y5=1: Yes y5=0: No BVector FSM not X2 and not X3 and X1 Count a3 a1 Index Count ++ Index ++ y3, y4 X2 Result: Yes y5 not X2 and X3 X1 No or Yes a4 a0 a1 not X2 and not X3 and not X1 Result: No Count = 0 Index = 0 y1, y2 1 a3 X2 not X1 a2 else Index ++ Count=0 y1, y4 reset = 1 1 a4 X3 X3 else X1 not X3 1 a1 X1 not X1 not X3 a2
y1: Count=0; y2: Index=0; y3: Count++; y4: Index++; y5=1: Yes y5=0: No BVector FSM not X2 and not X3 and X1 Count a3 a1 Index Count ++ Index ++ y3, y4 X2 Result: Yes y5 not X2 and X3 X1 No or Yes a4 a0 Result: No Count = 0 Index = 0 y1, y2 not X2 and not X3 and not X1 not X1 a2 Index ++ Count=0 y1, y4 reset = 1 X3 X1 not X3 not X1 not X3
BVector(Index) = 1 - X1 BVector(Index) = 0 - not X1 count=M - X2 countM - not x2 Index=N-1 - X3 Index N-1 - not X3 countM and IndexN and BVector(Index) = 1 a3 count=M Count ++ Index ++ Result: Yes countM and Index=N BVector(Index) = 1 a1 a4 a0 a1 countMand IndexN and BVector(Index) = 0 Result: No Count = 0 Index = 0 1 a3 X2 BVector(Index) = 0 a2 else Index=N Index ++ Count=0 reset = 1 1 a4 X3 else 1 a1 X1 BVector(Index) = 1 and Index N BVector(Index) = 0 and Index N a2
case FSMstate is when a0 => Count <= 0; Index <= 0; if BVector(0) = '1' then FSMnext_state <= a1; else FSMnext_state <= a2; end if; when a1 => Count <= Count + 1; Index <= Index + 1; if (Count = NumberOfSucOnes-1)then FSMnext_state <= a3; elsif (Index = SizeOfVector-1) then FSMnext_state <= a4; elsif (BVector(index+1) = '1') then FSMnext_state <= a1; else FSMnext_state <= a2; end if; a1 1 a3 X2 else 1 a4 a1 X3 BVector(Index) = 1 - X1 BVector(Index) = 0 - not X1 count=M - X2 countM - not x2 Index=N-1 - X3 Index N-1 - not X3 else Count ++ Index ++ y3, y4 1 a1 X1 a2
entity FSM_succeeding_ones is generic (AddressBits : natural; StateMaxValue : natural; NumberOfColumns : natural; SizeOfVector : natural; NumberOfSucOnes : natural ); Port ( ASCII_in : in STD_LOGIC_VECTOR (7 downto 0); ASCII_out : out STD_LOGIC_VECTOR (7 downto 0); Address_in : in STD_LOGIC_VECTOR (AddressBits - 1 downto 0); Address_out : out STD_LOGIC_VECTOR (AddressBits - 1 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC; WE_in : in STD_LOGIC; WE_out : out STD_LOGIC); end FSM_succeeding_ones; architecture Behavioral of FSM_succeeding_ones is signal BVector : STD_LOGIC_VECTOR(SizeOfVector-1 downto 0); -- Binary Vector signal YesNo: string(1 to 5) := " "; signal BVectorName: string(1 to 26) := "Given binary vector = "; constant TextOutBegin: string(1 to 11) := "Contains "; constant TextOutEnd: string(1 to 19) := " succeeding ones: "; signal count : integer range 0 to NumberOfSucOnes; signal index : integer range 0 to SizeOfVector; type state_type is (a0,a1,a2,a3,a4); signal FSMstate, FSMnext_state : state_type; begin BVector(conv_integer(Address_in(3 downto 0))) <= '0' when rst = '1' else ASCII_in(0) when ((ASCII_in >= "00110000") or (ASCII_in <= "00110001")) and (WE_in = '1'); -------------- FSM begin BVector FSM 0101110101101011 Count Index Exemplo: No or Yes A={ao,…,a4};
-------------- FSM begin process(clk,rst) begin if rst = '1' then FSMstate <= a0; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if; end process; process(clk,rst) begin if rst = '1' then YesNo <= " "; elsif falling_edge(clk) then case FSMstate is when a0 => Count <= 0; Index <= 0; if BVector(0) = '1' then FSMnext_state <= a1; else FSMnext_state <= a2; end if; Count ++ Index ++ 0 BVector(Index) = 1 a1 a0 Count = 0 Index = 0 0 BVector(Index) = 0 a2 reset = 1 Index ++ Count=0
when a1 => Count <= Count + 1; Index <= Index + 1; if (Count = NumberOfSucOnes-1)then FSMnext_state <= a3; elsif (Index = SizeOfVector-1) then FSMnext_state <= a4; elsif (BVector(index+1) = '1') then FSMnext_state <= a1; else FSMnext_state <= a2; end if; when a2 => Count <= 0; Index <= Index + 1; if (Index = SizeOfVector-1) then FSMnext_state <= a4; elsif (BVector(index+1) = '0') then FSMnext_state <= a2; else FSMnext_state <= a1; end if; when a3 => YesNo <= " Yes "; FSMnext_state <= a0; when a4 => YesNo <= " No "; FSMnext_state <= a0; when others => null; end case; else null; end if; end process; -------------- FSM end signal YesNo: string(1 to 5) := " ";
