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CSC 4250 Computer Architectures

CSC 4250 Computer Architectures. September 22, 2006 Appendix A. Pipelining. Instruction Issue. What is Instruction Issue? Process of letting an instruction move from ID stage to EX stage. Data Hazards. How does MIPS Integer Pipeline avoid data hazards?

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CSC 4250 Computer Architectures

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  1. CSC 4250Computer Architectures September 22, 2006Appendix A. Pipelining

  2. Instruction Issue • What is Instruction Issue? • Process of letting an instruction move from ID stage to EX stage.

  3. Data Hazards • How does MIPS Integer Pipeline avoid data hazards? • The pipeline checks data hazards during ID. If hazard exists, then pipeline stops instruction issue.

  4. Forwarding • Determine if forwarding is needed during EX • Set appropriate controls

  5. Data Forwarding to ALU inputs in EX

  6. More on Forwarding • There are 10 separate comparisons needed to tell whether a forwarding operation should occur. Remember that the pipeline latch for destination instruction in EX is ID/EX, while the source values come from the ALUOutput portion of EX/MEM or MEM/WB or the LMD portion of MEM/WB.

  7. Load Interlocks • Example: LD R1,45(R2) DADD R5,R1,R7 • How to detect need for Load Interlock?

  8. Logic to Detect Need for Load Interlocks

  9. Explanation of Previous Slide • Lines 1 and 2 test whether the load destination register is one of the source registers for an R-R operation in ID. Line 3 determines if the load destination register is a source for a load or store effective address, an ALU immediate, or a branch test. Remember that the IF/ID register holds the state of the instruction in ID, which potentially uses the load result, while ID/EX holds the state of the instruction in EX, which is the load instruction.

  10. Exception (also called interrupt or fault) Includes • I/O device request • Invoke OS • Breakpoint (programmer-requested interrupt) • Integer (FP) arithmetic overflow • Page fault (not in main memory) • Misaligned memory accesses • Memory protection violation • Use undefined or unimplemented instruction • Hardware malfunctions • Power failure

  11. Characteristics of Exceptions • Synchronous versus asynchronous (same place, same data and mem. location → synchronous) • User requested versus coerced (hardware event not under control → coerced) • User maskable versus user nonmaskable (event can be disabled by user → maskable) • Within versus between instructions (exceptions within instructions are usually synchronous) • Resume versus terminate (program’s execution continues → resume)

  12. Actions for Different Exceptions

  13. How to Save Pipeline State • Force trap instruction into pipeline on next IF • Until trap is taken, turn off all writes for faulting instruction and all instructions that follow in the pipeline • After exception-handling routine in OS receives control, it saves the PC of faulting instruction

  14. Delayed Branch • It is not possible to re-create the state of the processor with a single PC • Need to save and restore as many PCs as the length of the branch delay plus one

  15. Precise Exceptions • If the pipeline can be stopped so that the instructions just before the faulting instruction are completed and those after it can be restarted from scratch, the pipeline is said to exhibit precise exceptions

  16. Possible Exceptions in MIPS Pipeline

  17. Exceptions in MIPS • Multiple exceptions may occur in same clock cycle • Exceptions may occur out of order • Example: LD IF ID EX MEM WB DADD IF ID EX MEM WB LD may encounter a data page fault, while DADD gets an instruction page fault

  18. Out-of-order Exceptions • Say we want precise exceptions • DADD exception occurs first • Pipeline cannot handle DADD exception yet • Hardware posts all exceptions caused by a given instrution in a status vector associated with that instruction • Once exception set, stop register and memory writes • When instruction enters WB, status vector is checked • Exceptions handled in same order as unpipelined processor ─ exception in earliest instruction first

  19. MIPS Pipeline with Unpipelined FP Units

  20. MIPS Pipeline with two pipelined FP units

  21. Functional Units

  22. Hazards in Longer Latency Pipelines • Divide unit not pipelined → Structural hazards • Varying instruction running times → Multiple register writes in a cycle • Instructions don’t reach WB in order → WAW hazards • Instructions complete in order different from issue → Problems with exceptions • Longer latency of operations → RAW hazards more frequent • WAR hazards?

  23. Data Hazards • WAW Hazard ─ Write After Write Hazard • RAW Hazard ─ Read After Write Hazard • WAR Hazard ─ Write After Read Hazard • Is there a RAR hazard?

  24. Stalls from WAW Hazards • DIV.D F0,F4,F6 • ADD.D F10,F0,F8 • ADD.D F0,F12,F14 Clock cycle number In. 1 2 3 4 5 6 7 8 9 10 11 … 27 28 29 30 31 32 33 • IF ID D1 D2 D3 D4 D5 D6 D7 D8 D9 … D25 ME WB • IF • IF Fill in the blanks above

  25. Stalls from RAW Hazards • L.D F4,O(R2) • MUL.D F0,F4,F6 • ADD.D F2,F0,F8 • S.D F2,O(R2) Clock cycle number In. 1 2 3 4 5 6 7 8 9 10 11 … 27 28 29 • IF ID EX ME WB • IF • IF • IF Fill in the blanks above

  26. No WAR Hazards • WAR hazards are not possible, since the register reads always occur in the ID stage (as long as instructions are issued in order). • Example: ADD R1,R2,R3 IF ID EX ME WB ADD R2,R4,R5 IF ID EX ME WB

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