New Strategies for Radiation Hard Electronics

1. New Strategies for Radiation Hard Electronics Ronald Lacoe, Donald Mayer, Jon Osborn and Stephanie Brown Microelectronics Technology Department Laboratory Operations, The Aerospace Corporation 2001 MRQW December 11, 2001

2. Overview • Why rad-hard-by-design targeting commercial foundries now • “Push” from rad-hard foundries • “Pull” toward commercial foundries • Designing in radiation hardness • Where we are today – technically • Summary

3. 11 10000 1x10 DEC B SIA Roadmap Alpha Motorola 10 B J Sandia B 1x10 B B B 1000 Pentium B PowerPC B J J H H J J H J 9 Intel J 1x10 B B J RAD750 J H Pentium J DRAM H 100 NGSP B J H 8 Intel 1x10 PPC 603e B F 80x86 Memory Size, Bits Harris Lock-Mart Ñ Ñ Ñ Performance, MIPS 10 7 B 1x10 F RHC3001 RAD6000 SRAM B J H Ñ F 6 1x10 B J H Honeywell 1 Rad-Hard RH32 Honeywell B J H Intel 5 1x10 SRAM F GVSC 8008 B J H 0.1 4 B J H 1x10 1 B J 0.01 3 1x10 J 1970 1975 1980 1985 1990 1995 2000 2005 2010 1970 1975 1980 1985 1990 1995 2000 2005 2010 Year “Push” from Rad-Hard Foundries:Lagging Performance Microprocessors Memories Rad-Hard Lags 2-3 Generations Behind Commercial

4. “Push” from Rad-Hard Foundries:Disappearing Foundries 18 Upper-Hard 18 16 Total Dose Hard 14 12 11 11 10 National & UTMC 8 7 6 6 7 2 Digital /2 Analog BAES & Honeywell/ Intersil & ADI 4 4 4 2 0 1985 1985 1993 1993 1995 1995 1998 *DTRA 1999

5. “Push” from Rad-Hard Foundries:Low Volume Issues • Low volume foundries potentially have difficulty: • Achieving high yields • Maintaining process stability resulting in schedule slippage • Achieving competitive pricing

6. “Pull” Toward Commercial Foundries:Performance Ahead of 1999 SIA Roadmap 0.18 0.15 0.13 0.10 1999 SIA UMC Core Logic Roadmap

7. “Pull” Toward Commercial Foundries:Performance Ahead of 1999 SIA Roadmap TSMC Core Logic Roadmap

8. “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Gate Oxide Threshold Voltage Shifts • Gate oxide threshold voltage shifts depends on the square of the gate oxide thickness: • each technology generation jump, oxide thickness decreases  radiation-induced threshold voltage shifts decrease • For tox~ 50Å, quantum mechanical tunneling dominates and expect negligible threshold voltage shifts • Difficult to design around gate oxide threshold voltage shifts

9. 100 1000 HP 0.5 µm HP 0.5 µm É É É Ñ Orbit 1.2 µm Ñ Orbit 1.2 µm Ñ Ñ Ñ 100 É É É AMI 1.6 µm Ñ É 3 3 3 AMI 1.2 µm Ñ 10 3 Ñ É Ñ É HP 0.8 µm Ñ 3 É HP 0.8 µm É 10 Delta Threshold Voltage/t2 Delta Threshold Voltage/t2 Ñ 3 Post- Ñ 3 post- É 1 Anneal É anneal 3 Slope = 1 1 Ñ É slope = 1 3 Ñ Ñ 0.1 0.1 1000 1000 1 10 100 1 10 100 0 Dose (krads) Dose (krads) PMOS NMOS “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Gate Oxide Threshold Voltage Shifts Decrease in DVT due to thinner oxides, not “better” oxides

10. Primary Electron n+ Drain Current Flow Polysilicon Gate Field Oxide Edge Current Components n+ Source “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness-- Isolated Transistor Edge Leakage • As technology scaled, transitioned from standard LOCOS recessed LOCOS  shallow trench isolation (STI) • Unintended consequence of this scaling is improved edge total dose hardness  less edge leakage • reduces/eliminates “birds beak” region at edges

11. Chartered 0.35 NMOS Transistor TSMC 0.25 NMOS Transistor 1E-04 1E-03 NMOS 1E-05 1E-06 0 1E-07 Ids(A) 1K 1E-08 Ids (A) 3K 10K 1E-09 30K .E-10 50K 70K 1E-11 0 100K 1E-12 300K 50K 1E-13 Post-Anneal 100K 1E-14 250K 1E-15 -0.5 0 0.5 1 1.5 2 2.5 -0.5 0 0.5 1 1.5 2 500K GateVoltage (V) TMSC 0.18 NMOSTransistor Gate Voltage (V) 750K 1E-03 1000K -0.5 0 0.5 1 1.5 2 1E-05 0 1E-07 Ids (A) 50K 100K 1E-09 150K 200K 1E-11 250K 300K 1E-13 400k 500k 1E-15 Gate Voltage (V) “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolated Transistor Edge Leakage • Thinner gate and isolation oxides results in less hole trapping • Isolation oxides process and quality increasing as go from LOCOS to Recessed LOCOS to STI technologies

12. “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolation Oxides • Isolation oxides are thick oxides, and hence, can trap lots of holes, resulting in large VT shifts • If shift sufficient such that inversion occurs at or below the operating voltage, can degrade interdevice isolation • Data to date suggests this is the weak-link from a total dose hardness viewpoint

13. 1E-03 72 rd/s 2.5 V 1.01 0 1E-05 10 krad 1 50 krad 0.99 100 krad 1E-07 300 krad C/Cmax Ids (A) 0.98 0 0.97 1E-09 10krd 50krd 0.96 100krd 1E-11 0.95 Post-Anneal -50 -40 -30 -20 -10 0 10 20 30 40 50 Gate Voltage (V) 1E-13 -10 0 10 20 30 40 50 60 70 Gate Voltage (V) “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Isolation Oxides TSMC 0.25 Recessed LOCOS Chartered 0.35 Recessed LOCOS

14. 3.0 Post Anneal NAND Post-Anneal 100 NOR 2.5 INVERTER Power (mW) NAND Delay (ps) NOR INVERTER 2.0 50 2.5V/2.5V 2.5V/2.5V 1.5 0 0 1 2 3 4 0 1 2 3 4 Dose (Mrd) Dose (Mrd) “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Dynamic Operation TSMC 0.25 No change in power-delay product up to 3 Mrad(Si)

15. “Pull” Toward Commercial Foundries:Trend Toward Increased Total Dose Hardness--Self Annealing • Data indicates for both edge leakage and isolation oxide, get nearly full recovery after a biased high-temperature anneal • Indicates most of the radiation induced degradation is associated with low-energy-trapped charge • In space, natural dose rate is at least 10,000 x lower than that used during Mil. Std. 1019 testing dose rate • When factor in annealing, can get substantial increase in process total dose hardness

16. Threshold Voltage Maximum Drive Current Mean (µA) Std. Dev. (µA) Max (µA) Min (µA) Mean (mV) Std. Dev. (mV) Max (mV) Min (mV) 282.15 5.66 293.67 272.75 727.66 11.22 755.27 712.98 “Pull” Toward Commercial Foundries:Well-Controlled Processes HP 0.5

17. Overview • Why rad-hard-by-design targeting commercial foundries now • Designing in radiation hardness • Total Dose, SEE, SEL, and Prompt Dose • Performance Comparison • Two Approaches • Where we are today • Summary

18. Designing In Radiation Hardness:Approach • Leverage intrinsic total dose hardness and performance of commercial foundries • Use design techniques to • Achieve additional total dose hardness • Mitigate against single event effects • Mitigate against prompt dose effects

19. 1E-03 source 72 rd/s 2.5 V 1E-05 gate 0 1E-07 drain 100 krd Ids (A) 250 krd 1E-09 500 krd 1E-11 1 Mrd Annular Transistor 2 Mrd 1E-13 Post-Anneal 1E-15 Gate -0.5 0 0.5 1 1.5 2 Drain Source Gate Voltage (V) Standard Edged Transistor Designing In Radiation Hardness:TID Hardness--Annular Transistors TSMC 0.25 • Off-state leakage remains low • Increased die size • Only needed for NMOS

20. Designing In Radiation Hardness:TID Hardness--Guardbands • P+ guardband around NMOS devices prevents interdevice leakage by locally increasing the isolation oxide threshold voltage • Pay an area penalty that depends on foundry design rules and implementation strategy

21. Designing In Radiation Hardness:SEE Mitigation • As CMOS technology is scaled, individual nodes of data latches become more susceptible to upset • Decreased charge storage capacitance and supply voltage  decreased SEU threshold ??  increased SEUs ?? • Single-event upset mitigated with design and process techniques • Rad-Hard foundries use either resistive damping, capacitive damping, or redundancy in design techniques • Commercial foundries, in general, do not support resistor fabrication for resistive damping

22. Redundant Latch Error Detection And Correction Triple Modular Redundancy Standard (6 xtors) Redundant (14 xtors) Designing In Radiation Hardness:SEE Mitigation Techniques Univ. of New Mexico HP 0.35 mm, 0.5 mm LET>160 MeV/mg-cm2

23. Designing In Radiation Hardness: Single-Event Latchup • Commercial foundries address and design to prevent against latchup during circuit operation • As devices are scaled, Vdd is lowered which helps mitigate against latchup • Once Vdd is below the sustaining voltage for latchup, latchup cannot occur • Many commercial parts do not latchup in a space environment • Latchup hardness can be enhanced with process changes • Epitaxial starting material can reduce series resistance

24. AMI 1.6 Orbit 1.2 HP 0.5 35 26.57 24.11 pJ 30 22.95 20.19 18.99 25 20 12.33 SEL Threshold, 10.6 15 8.2 7.61 10 2.86 2.07 5 0 None (Min) n+ p+ Dual n+/p+ Designing In Radiation Hardness: Single-Event Latchup Mitigation • Latchup hardness can be enhanced with design techniques • Well separation or guardbands can suppress positive feedback path • Multiple ground contacts can reduce series resistance Guardbands can significantly improve latchup hardness of CMOS integrated circuits NAND Gate Standard Guardbands

25. Designing In Radiation Hardness: Prompt Dose Issues • Design to avoid rail span collapse • Well contacts • Wide and/or redundant power and ground busses • Bulk CMOS processes limited to about 5E9 rad/sec ? operate through levels • Need SOI or SOS to achieve > 1E10 rad/sec • Minimal hardware with operate-through requirements • Potential foundries with SOI/SOS capabilities • Peregrine (SOS) - SPAWAR (SOS) • DMEA (SOS) - Lincoln Labs (SOI) • Sandia (SOI) - Commercial SOI (?) • Honeywell (SOI)

26. Designing In Radiation Hardness: Performance Comparison 2.3x Area 1.7x Area 2NAND Logic Gate Edgeless Transistor 1x Area Widened Busses Guard Bands Rad-Hard-By-Design 0.35-mm Comm. Std. Design 0.50-mm “Rad-Hard” Std. Design 0.35-mm Comm.

27. Designing In Radiation Hardness: Selected Performance Parameters HP HP HP 2NAND Logic Gate 0.35 µm 0.35 µm 0.5 µm Parameter Commercial RHBD* "Rad-hard" Lambda, µm 0.20 0.20 0.30 2 Cell area, µm 51.00 88.44 114.75 W/L(n) 5.00 12.00 5.00 W/L(p) 9.00 20.00 9.00 Supply voltage, V 3.30 3.30 5.00 Propagation delay, ns (FO=2) 0.10 0.09 0.14 Power dissipation, µW/MHz 0.29 0.64 1.10 Power delay product, aJ/MHz 38 80 168 2 Gate density, Mgates/cm 1.96 1.13 0.87 Maximum operating frequency, MHz 376 402 328 2 Throughput per watt, Mgates-MHz/cm /µW 6.82 1.75 0.79 *Rad-Hard-By-Design (RHBD)

28. Wide range of cell libraries possible (but not required) to reflect varying mission environments and threats Can optimize cell libraries for specific missions at the cost of multiple library development Two extremes Maximum performance approach Accept intrinsic radiation hardness of commercial process Use foundry standard cell library Foundry does layout and verification Lower risk approach High Margin approach Use aggressive design techniques to further mitigate against total dose, SEE and weapon effects Requires custom standard cell library Layout and verification done by contractor Higher risk approach Designing In Radiation Hardness: Cell Libraries

29. Overview • Why rad-hard-by-design targeting commercial foundries now • Designing in radiation hardness • Where we are today • Total Dose • SEE • Prompt Dose • Reliability • Conclusions

30. Where We Are Today:Total Dose • Efficacy of annular transistors and guardbands demonstrated at the single transistor level • CERN is building approximately 100 large ASICS for the Large Hadron Collider Experiment • Employ annular transistors and p+ guardbands • Driven to approach by cost and performance advantages over rad-hard approach • Using the IBM 0.25 mm process • Largest circuit to date contains 13 million transistors • Pixel Readout Integrated Circuit (ROIC) • Not yet established what the density, power, and performance impact of RHBD will be

31. Where We Are Today:Single Event Effects • Long history of using design approaches for mitigating against Single Event Effects at the Rad-Hard Foundries • Design-hardened latches have been demonstrated (UNM) with greater than 160 LET SEU thresholds • The potential and limitations of system level approaches to achieve SEU hardness, such as EDAC and TMR, have not been well explored at the chip level • Mitigation against Single-Event-Transients (SETs) remains a challenge for both RH and RHBD approaches

32. Where We Are Today:Prompt Dose • Data supports hardness of 5E9 rad/s in bulk CMOS • Can we go higher? • Generally believed to achieve hardness greater than 1E10 rad/s, need an insulating substrate technology • Three components to prompt dose mitigation: circuit design, wafer technology, circuit fabrication process • With RHBD, control design • May be able to get foundry to allow user-supplied wafers • Cannot control process • Design approaches well understood, but have not been implemented in large scale circuits at commercial foundries

33. L=0.18 micron 100 Vd=2.75V Vd=2.25V 10 Decease in Gmmax (%) 1 0.1 1.E+00 1.E+02 1.E+04 1.E+06 Stress Time (s) Where We Are Today:Hot-CarrierReliability TSMC 0.18 1.8 V 10 yrs

34. Conclusion • Market forces driving space technology toward commercial part performance • Trend toward increased total dose hardness in commercial CMOS foundries increases the attractiveness of a RHBD approach • RHBD techniques have been demonstrated for TID, SEE, and Prompt-Dose Mitigation at the device level, but validation not yet complete

35. Backup Slides

36. Selected Performance Parameters

37. Device Type Terminal Max Trapped Charge Min Trapped Charge Max Interface States Min Interface States NMOS - Gate Vdd Gnd Vdd Gnd NMOS - Drain Gnd Vdd Gnd Gnd NMOS - Source Gnd Vdd Gnd Gnd NMOS - Substrate Gnd Gnd Gnd Gnd PMOS - Gate Vdd Gnd Vdd Gnd PMOS - Drain Gnd Vdd Gnd Vdd PMOS - Source Gnd Vdd Gnd Vdd PMOS - Substrate Vdd Vdd Vdd Vdd Impact of Bias Conditions on TID Mechanisms* * DR Alexander and DG Mavis, “Design Issues for Radiation Tolerant Microcircuits in Space,” 1996 IEEE NSREC Short Course