ECE 345 Professor Swenson TA: Ajay Patel

1. The Wireless Clock Updater ECE 345Professor SwensonTA: Ajay Patel Presented by: Amit Nainani and Tim Mosher May 3, 1999

2. Objective • Design and implement a means of updating a digital remote clock from a fixed transmitter site

3. Why we chose this project • Interest in RF circuit and antenna design and DSP • Marketability • Gain both hardware and software design experience

4. Advantages • Bypass the need for manual labor currently used for setting clocks on a large scale • Easily reset clocks after daylight savings time changes and power outages • Ensure precise clock synchronization • Inexpensive receiver circuit to replace existing manual clocks • Ease of modification through software

5. Original Design

6. Initial Concerns • Frequency of operation • FCC Licensing • High frequency design concerns • Time considerations • Original plan would include design of transmitter, receiver, antennas, and programming a DSP processor.

7. Suggestions • Use Motorola HC11 microcontroller in place of DSP processor • Recommended to us as easier to implement than a DSP microprocessor • Sufficient for our implementation • Disadvantage: Higher bandwidth

8. Suggestions • Linx modules • Inexpensive transmitter-receiver solution • No need of FCC licensing at 418 MHz • Direct interface to microcontroller

9. Block Diagrams Transmitter System Receiver System

10. Error Detection • Possible Error Detection Schemes • Send data multiple times • Parity (even or odd) • Hamming Error Detection

11. Error Detection • Incorporate a Hamming error detection scheme • Advantages • Will identify a single error in a particular information packet • Whereas parity checking only identifies an error, the Hamming scheme actually corrects the error bit

12. Error Detection • Disadvantages of Hamming error detection scheme • If more than 1 error occurs in the packet, the errors will go undetected and result in incorrect decoding of the data packet • More complex and difficult to implement in software

13. Hamming Error Detection • # of Information Symbols: • Code Length: • # of Check Symbols: • To transmit 11 bits satisfying the above criteria, find that: • k = 11 (11 information bits) • m = 4 (4 check bits) • n = 15 (15 total bits in transmitted message)

14. Parity Check Matrix (H) • We created the following H matrix by following the following guidelines: • The columns of T are of weight 2 or more. • The rows of H have minimum distance 3.

15. Generator Matrix (G)

16. Multiplication by G

17. Transmit Software Perform Modulo 2 Sum for each of the 4 columns of “AND”ed bits Load 1st column of G matrix into Accumululator Store Result in Memory AND Accumulator contents with time bits Repeat Above Steps for Next 3 Columns of G Matrix Append check bits onto time bits for transmission

18. Syndrome Calculation

19. Syndrome and Coset Leaders

20. Receiver Design • Accept incoming 15 bit message signal from the transmitter • Multiply the bit string by the transpose of the H matrix • Sum to produce the four syndrome bits • Use syndrome to look up coset leader • Add corresponding coset leader to incoming message signal to produce correct signal

21. Receiver Software Multiplying incoming message by HT AND error bits with contents of accumulator AND Hr bits with contents of acc A AND minute bits (6) bitwise with acc A AND AM/PM bit with contents of acc A Move result from acc A into memory location Move result from acc A into memory location Store results from acc A into memory Clear acc A Clear acc A Clear acc A Load next 6 bits of column of HT into acc A Load next 4 bits of column of HT into acc A Load last bit from column of HT into acc A

22. Receiver Software Using the syndrome to find the correct coset leader S= (0011) S= (0000) C YES B Load 00001000 into acc A Load 1 into acc A S= (0100) YES C XOR acc A with check bits (error bits), performing bitwise addition Add acc A to the original AM/PM check bits B NO B 5 Return to beginning of code to await next set of message data Send corrected data to LED decoder

23. Hardware Schematic

24. Hardware Schematic (TX Side)

25. Problems • Software • Learning to code in assembly • Initializing the stack pointers • Infinite loops due to returns from subroutines • Working with long strings of 1’s and 0’s • Regulating execution time

26. Problems(cont) • Hardware • Availability of micro-controllers • Burning up of chips due to fluctuating voltages • Malfunctioning output ports • Linx module phase latch-ups • External interference

27. Antenna Design Considerations • Desired Antenna Characteristics • Omni-directional pattern • Input Impedance between 48-52 ohms for good match to RG58-U 50 ohm coax • SWR<1.5 at center design frequency (418 MHz) • To achieve these desired characteristics, we decided on a quarter-wavelength groundplane

28. Antenna Design Considerations • Element Length Calculation (actually cut a length of wire 1 inch longer than calculated for tuning purposes)

29. Antenna SWR Characteristics

30. Tests • Modular testing of code • SWR tests of antennas • Ports A, B and C • Transmission tests on encoded data • Deliberate error insertion to demonstrate error correction scheme.

31. Cost Analysis • Anticipated Total Parts Cost: $190.00 • Actual Total Parts Cost: $161.93

32. Cost Analysis • Proposed Labor Costs: • Total Antic. Labor Cost = 2.5 * $7500 = $18,750 • Actual Labor Cost: • Total Actual Labor Cost = $17,500

33. Cost Analysis • Total Anticipated Costs: $18,940 • Total Actual Costs: $17,661.93 • Budget Surplus: $1,278.07