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3D R G B LED Cube

3D R G B LED Cube. Group 15 Luke Ausley BSEE Joshua Moyerman BSPE Andrew Smith BSPE Sponsored by Stellascapes. Motivations and Goals. Desire to discover innovative methods for improving LED cube design Project aligned with individual group member’s expertise and interest

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3D R G B LED Cube

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  1. 3D RGBLED Cube Group 15 Luke Ausley BSEE Joshua Moyerman BSPE Andrew Smith BSPE Sponsored by Stellascapes

  2. Motivations and Goals • Desire to discover innovative methods for improving LED cube design • Project aligned with individual group member’s expertise and interest • Diverse design aspects

  3. Specifications

  4. High Level Diagram

  5. High Level Work Distribution

  6. Hardware Block Diagram

  7. Key Hardware Design Decisions • Multiplexing • Control Hardware Structure • Joint FPGA/MCU • LED Driver Board • TI LED Drivers • MOSFETs • PCB Layout • Three separate two-layer PCBs

  8. Driver Design • Two identical driver boards will be used to reduce power dissipation and circuit board size and isolate faults. • TLC5948A LED Drivers • SI4101DY-T1-GE3 P Channel Mosfet • Individually fused planes

  9. Driver Schematic

  10. Driver PCB Layout

  11. Control Design • FPGA and MCU based control system • FPGA to handle interfacing to driver circuitry due to timing constraints • MCU to handle user interfacing via ethernet • FPGA and MCU will work together to complete the task of driving LEDs

  12. FPGA and MCU Choice • PIC24HJ265GP206A Microcontroller • Low cost, 16 bit architecture • Stellascapes existing experience with Microchip line of products • Readily available ethernet interface with TCP/IP Stack • Xilinx XC3S200AVQ100 Spartan 3A FPGA • Team’s familiarity with Xilinx ISE from Digital Systems Lab work • Stellascapes interest in integrating FPGA with PIC24

  13. Control Schematic

  14. Control PCB Layout

  15. PCBs Interfaced

  16. Firmware - MCU • Developed using C (6000 lines of code) • Microchip MPLAB X IDE • Microchip XC C Compiler • Microchip’s freely available TCP/IP Stack

  17. Firmware - FPGA • Written in Verilog (1600 lines of code) • Xilinx ISE 14.5 Development Environment • Simulated using ISim

  18. Firmware Update Cycle • Updated FPGA code to be loaded via MCU Ethernet connection • FPGA bitstream stored on 8Mb EEPROM • MCU to control loading of FPGA Device

  19. Power Supply • Ablecom SP502-2S

  20. Construction

  21. Construction

  22. Prototype

  23. Software

  24. Software Design Choices • Developed in Microsoft Visual Studio Environment (3200 lines of code)

  25. Software Block Diagram

  26. Animation Class Diagrams

  27. LED Animation GUI • 12 distinct animations • 3 distinct color modes • User Input • HSV Scroll • Random • 24-bit color palette • Brightness scaling

  28. Communication • E1.31 Streaming Architecture for Control Networks (sACN) • Up to 512 color channels/packet • Animation data sent over 6 packets

  29. Simulators

  30. Hardware Simulator Sine Ripple Random Color Rotating Sine HSV Scroll Color Scrolling Text User Input Color

  31. Firmware Simulator

  32. Budget

  33. Challenges • Production delays • FPGA/Microprocessor interfacing

  34. Successes • All components operational in standalone • Mature black-box software • Timing specs met • Proof of concept with moderate confidence • Functional prototype

  35. Special Thanks • Stellascapes • Sponsorship

  36. Questions?

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