Microprogramming and Exceptions 14 October 2013

1. CDA 3101 Fall 2013Introduction to Computer Organization Microprogramming and Exceptions 14 October 2013

2. Review • Multicycle Datapath – 1 cycle per execution step: • Instruction Fetch • Instruction Decode / Data Fetch • ALU op / R-format Execution • R-format Completion • Memory Access Completion • Finite-State Machine • Current State, Next State, Transition Function • Finite-State Control • State: Control Signals Asserted • Arc: Requirements for Transition • Can be implemented in hardware (ROM, PLA)

3. Overview • Problems with Finite-State Control • Real processors have Hundreds of States • Thousands of interactions between states • FSC graphical design too small for realistic architectures • Solution: Microprogramming • Software-based control design • Control signals => fields in microinstruction • Sequence microinstructions => microprogram • Challenges of Microprogramming • Microinstruction design and sequencing • Exception handling

4. MIPS Microinstruction Format Microinstruction: Abstraction of datapath control FieldSpecifies • ALU control ALUop for this clock cycle • SRC1 Source for first ALU operand • SRC2 Source for second ALU operand • Register Control Register read/write, data value written • Memory Memory read/write, data value written Destination register for MemRead • PCWrite control Source for PC (PC+4, BTA, JTA) • Sequencing How to choose next microinstruction

5. Sequencing Modes Specifies how to choose the next microinstruction • Incrementation – If current microinstruction at address A, then get the next 32-bit instruction from A + 4 (value = Seq) • Branching – Go to the microinstruction that fetches the next MIPS instruction (value = Fetch) • Control-Directed Choice – Choose next microinstruction based on control input (value = Dispatch i) Dispatch Tables: • Like a jump table in MIPS programming • Tell microprogram control where to go to execute a prespecified routine (e.g., a utility program for data fetch)

6. Instruction Fetch and Decode Microinstructions: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing Fetch Add PC 4 --- Read PC ALU Seq --- Add PC Extshft Read --- --- Dispatch 1 Actions: • ALU adds PC+4, puts ALUout in PC, gets next microinstruction • ALU adds PC and sign-extended shifted offset to compute BTA, then reads data from register file into buffers A and B

7. Memory Access Microinstructions: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing Mem1 Add A Extend --- --- --- Dispatch 2 LW2 --- --- --- --- Read ALU --- Seq --- --- --- --- Write MDR --- --- Fetch Actions: • ALU adds base in A + sign-extended offset => Memory address • For load, memory is read at address = ALUout • The output of memory is put in the memory data register (MDR) (Store instruction is symmetric)

8. R-format Execution Microinstructions: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing Rformat1 Func code A B --- --- --- Seq --- --- --- --- Write ALU --- --- Fetch Actions: • ALU op specified by funct field of instruction operates on A and B – Result goes to ALUout • The result in ALUout is written to the register file and we branch back to the calling point to get the next MIPS instruction

9. Branch and Jump Microinstructions: Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing Beq1 Subt A B --- --- ALUout-cond Fetch Jump1 --- --- --- --- --- Jump address Fetch Actions: • Branch subtracts A-B in ALU to set Zero output high if A=B, then jumps to BTA computed during instruction decode step • Jump transfers control by writing the JTA into the PC • Both microinstructions return to the point from which their dispatch table entry was called (e.g., Beq1 or Jump1 call)

10. Completed Microprogram • Dispatch Table 1: Mem1, Rformat1, Beq1, Jump1 • Dispatch Table 2: LW2 (load), SW2 (store)

11. Microprogramming Issues • Hardware Implementation • Similar to Finite-State Control • Current State in Register, Transition Function in ROM, PLA • Difference: mprog sequencer uses a c o u n t e r • Fallacy: Microprogram is faster • Olden Days: Microprogram store was fast memory • Today: Cache used, no performance advantage • Basis: Easier to modify software than hardware • Fallacy: New microinstructions are “free of charge” • Microprogram memory might not be full (at first) • Extra add-on instructions have to be supported in future rev’s.

12. New Topic: Exceptions Definition: Event causes unexpected transfer of control Types: (1) Exception [overflow] (2) Interrupt [I/O] Difference:Exception generated inside the processor Interrupt associated with external event Challenges: • Exception Detection – How to discover exception • Exception Handling – What to do MIPS: 2 types – Undefined instruction, Arith. overflow

13. Exception Detection • Undefined Instruction: • Add State 10 [Exception] to Finite-State Control • Every instruction not lw, sw, beq, R-format, or jump transitions to State 10 • Arithmetic Overflow: • Recall: ALU has overflow detection logic. So, create a new State 11 in FSC to handle overflow • When ALU output Overflow is asserted, then control is transferred to State 11

14. Exception Handling • Two Techniques:EPC/Cause and Vectored Interrupts • Vectored Interrupts: • Each exception has a distinct address AE associated with it • Exception detected => AE for that exception written to PC • EPC / Cause: (MIPS practice) • Exception detected => Address of instruction saved in $epc Cause register has code for exception 2. Exception handler acts on Cause, tries to restart execution at instruction pointed to by $epc

15. Mods to MIPS DP for Exceptions • New Registers - $epc and Cause (32-bit) • New Control Signals – EpcWrite, CauseWrite • New Control Line – 0 for undefined instr., 1 for ovflw • New Mux Signal for PCsource = 112 • Old PC inputs: PC+4, BTA, JTA • Additional input: AE = C000000016 in MIPS Recall: ALU overflow detection already “installed”

16. New Exception Handling States

17. New FSC with Exception States

18. New MIPS Multicycle Datapath Exception HW

19. Problems with Exceptions • Rollback and Restart • Rollback: Reverse effects of the process • Restart: Do a process or operation over again • Overflow exception detected after ALUout written • This means ALU operation produced an uncorrected error  • Current FSC does not support process restart or rollback How to Fix? • Not easy – Control system design is difficult – Requires much additional HW to do rollback

20. Conclusions • Microprogramming – More tractable for large ISAs • Challenge: Getting the fields and signals consistent • Pitfall: Microprograms not necessarily faster • Pitfall: Add-on microprogram instructions not “for free” • Exceptions (internal event) vs. Interrupts (external) –Exception Detection needs Special Hardware –Exception Handling needs more hardware ($$$$) Reminder: Friday 25 Oct 2012 :Exam-2

21. Exam-2 (Fri 25 Oct) Will Cover… • MIPS programs, Pointers and Arrays • Arithmetic/Logic operations, ALUs, MIPS ALU • Boolean Arithmetic (signed and unsigned +, -, x, /) • Floating Point Operations and IEEE 754 Standard • Next Topic: Pipeline!!