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SoC Test Strategies

SoC Test Strategies. 陳亮宙 R91943049 林學世 R91943073 王偉民 R91943085 92.06.10. Basic Concepts (1/2). __number of detect faults__. ‧Fault Coverage =. number of total faults. ‧Single Stuck-at Fault.

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SoC Test Strategies

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  1. SoC Test Strategies 陳亮宙R91943049 林學世R91943073 王偉民R91943085 92.06.10

  2. Basic Concepts (1/2) __number of detect faults__ ‧Fault Coverage = number of total faults ‧Single Stuck-at Fault One signal line in Boolean network of elementary gates is fixed to logic 0 or 1, independent of logic values on other signal lines ‧Test Pattern Input Boolean values for specific faults ‧Automatic Test Pattern Generation (ATPG) Generate test patterns for a netlist based on a given fault model

  3. Basic Concepts (2/2) ‧Scan Stitch memory elements into shift registers.

  4. Cost of Manufacture & Testing

  5. SoC Test Challenges ‧Fault coverage not enough ‧Delay and bridging defects more dominant ‧Single stuck-at fault model not enough ‧Hidden cores not easily accessible

  6. Digital Logic BIST and Circuit Under Test

  7. Pattern Generator ‧ROM ‧Algorithm ‧Exhaustive or Pseudo Exhaustive ‧Pseudo Random -Linear Feedback Shift Register (LFSR)

  8. Random Pattern Generator

  9. Response Analyzer

  10. Example of Response Analyzer

  11. Disadvantage of LFSR ‧Aliasing ‧Expensive ‧Fault coverage not enough

  12. Why MBIST ‧high density ‧a lot of I/O pins ‧regular

  13. Memory BIST

  14. Different Designs ‧black box ‧pass through ‧bypass-only ‧bypass ‧scan wrapper ‧universal test interface (UTI)

  15. Compare

  16. MBIST Automation Tool

  17. Analog and Mixed-Signal Test ‧Reconfiguration ‧Insert test point ‧Insert DAC or ADC

  18. IEEE 1500

  19. Test Access Mechanism (TAM) Distributed type Muxed type Daisy Chain

  20. SoC Test Schedule

  21. Conclusions ‧Testing important for SoC ‧BIST is necessary

  22. Reference ‧張永嘉,“SoC Test Strategies”,2002 ‧張永嘉,“Digital Logic BIST”,2002 ‧張永嘉,“Design Automation of Memory BIST”,2002 ‧M.L. Bushnell and V.D. Agrawal,“Essentials of electronic testing,” Kluwer Academic Publishers, 2000. ‧Koranne, S. ; Iyengar, V., “On the Use of k-tuples for SoC Test Schedule Representation”. Proc. IEEE Intl. Test Conf. (ITC), pp. 539 –548 , 2002.

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