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Learning SystemC

Learning SystemC. Freeha Azmat Saba Zia Dec 02, 2008. Agenda. Installation Introduction From Verilog to SystemC Counter as an Example Complete SystemC Modeling. Installation on Linux. Download System2.2 from www.systemc.org Run following commands in terminal cd systemC-2.2

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Learning SystemC

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  1. Learning SystemC Freeha Azmat Saba Zia Dec 02, 2008

  2. Agenda • Installation • Introduction • From Verilog to SystemC • Counter as an Example • Complete SystemC Modeling

  3. Installation on Linux • Download System2.2 from www.systemc.org • Run following commands in terminal • cd systemC-2.2 • mkdirobjdir • cdobjdir • setenv CXX g++ • ./configure • Gmake debug • Gmakeinstaal • Gmake check • Download dinotrace from www.veripool.com/dinotrace • tar xvfdinotrace*.tg*z • cddinotrace* • ./configure • make • # Test ./dinotrace traces/ascii.tra • make install

  4. Introduction : System C : • Is a C++ Library for system Level Modeling • Supports various abstraction Layers System C is used for : • Fast and efficient designs • System verification

  5. SystemC VS C++ C ++ System C • Sequential Language • Not suitable for complex and detailed systems • Data Types are not suitable for Hardware Implementation • Parallel Processing is possible • Incorporate delays, Clocks or Time • Data Types dedicated to Hardware modeling e.g bit, vector types as well as fixed point types.

  6. SystemC implementation • Modules • Processes • Ports and Interfaces • Channels

  7. Modules : • Is a C++ Class • Encapsulates hardware /software description • Any Modules has to be derived from the existing class sc_module. • SystemC modules are analogous to verilog modules or VHDL entity / architecture pair. • Modules communicate to other modules via ports.

  8. Ports and Interfaces : • Ports are defined as objects inside a module • Publically available to the outside world through the use of public Keyword. • Predefined Ports: sc_in<>,sc_out<>,sc_inout<>,sc_fifo_in<>,sc_fifo_out<> Example :sc_in<bool>clk; • User Defined Ports are defined with the help of sc_port class Example:Sc_port <sc_signal_in_if<bool>, 1> clk;

  9. Processes : • Two kinds of Processes : SC_METHOD: • cannot be suspended during its execution • Once the execution of SC_METHOD as been performed it halts and waits for new activities on its sensitivity list Similar to Verilogalways block SC_THREAD : • Can be suspended during execution and resumed at a later stage • SC_THREAD only executes once during simulation and then suspends Similar to Verilog initial Block

  10. Channels : • SystemC ‘s communication Medium. • Modules communicate via ports and channels • They are similar to Verilogwire and VHDL signal • System C provides a exhaustive range of pre-defined channels for generic uses such as sc_signal. • This Feature of language differentiate it from VHDL and Verilog

  11. From Verilog to SystemC module name(); // module functionality endmodule SC_MODULE(name) { //module functionality } input A,B; output F; reg [3:0] G; sc_in<bool> A,B; sc_out<bool> F; sc_uint<4> G; always @(posedgeclk) begin //process sensitive //to rising edge of clock //input end SC_CTOR(name) { //process to execute SC_METHOD(myfunc); //sensitive to clock sensitive<<clk.pos(); }

  12. From Verilog to SystemC add inst ( .F(F), .A(A), .B(B) ); add inst; SC_CTOR(name):inst(“INST”) { inst.A(A); inst.B(B); inst.F(F); } always @ () begin end SC_METHOD(myfunc); Initial begin end SC_THREAD (myfunc);

  13. Counter #include <systemc.h> SC_MODULE(counter){ sc_in_clkclk; sc_in<bool>reset; sc_out<sc_uint<4> > counter_out; sc_uint<4> count; SC_CTOR(counter) { SC_METHOD(myfunc); sensitive<<clk.pos(); sensitive<<reset; } void myfunc() { count=0; if(reset.read()==1) counter_out.write(count); else count =count + 1; counter_out.write(count); cout<<counter_out.read()<<endl; } }; intsc_main(intargc,char *argv[]){ counter c("hello"); c.myfunc(); sc_start(); return(0); } module counter(clk,reset,counter_out); input clk; input reset; output [3:0]counter_out; reg [3:0]counter_out; always @(posedgeclk or negedge reset) begin if(!reset) counter_out<=0; else counter_out<=counter_out + 1; end endmodule

  14. Complete SystemC Model REF:Introduction to SystemC by DeianTabakov Rice University Houston, TX

  15. Stimulus Generator /************************stimulus.h *********************/ #include "systemc.h" SC_MODULE(stim) { sc_out<bool> A, B; sc_in<bool> Clk; void StimGen() { A.write(false); B.write(false); wait(); // wait for the next clock tick A.write(false); B.write(true); wait(); // wait for the next clock tick ... sc_stop(); // notify kernel to stop simulation } SC_CTOR(stim) { SC_THREAD(StimGen); sensitive << Clk.pos(); } }; REF:Introduction to SystemC by DeianTabakov Rice University Houston, TX

  16. Monitor /************************monitor.h *********************/ #include "systemc.h" SC_MODULE(mon) { sc_in<bool> A, B, F; sc_in_clk Clk; void Monitor() { while(1) { wait(); cout << sc_time_stamp() << "\t " << A.read() << " " << B.read() << " " << F.read() << endl; } } SC_CTOR(mon) { SC_THREAD(Monitor); sensitive << Clk.pos(); cout << "Time\t A B F" << endl; } }; REF:Introduction to SystemC by DeianTabakov Rice University Houston, TX

  17. Complete XOR Model #include "stim.h" #include "exor.h" #include "mon.h“ int sc_main(int argc, char* argv[]) { sc_signal<bool> ASig, BSig, FSig; sc_clock TestClk("TestClock", 10, SC_NS, 0.5); stim Stim1("Stimulus"); mon Monitor1("Monitor"); Stim1.A(ASig); Monitor1.A(ASig); Stim1.B(BSig); Monitor1.B(BSig); Stim1.Clk(TestClk); Monitor1.F(FSig); Monitor1.Clk(TestClk); exor DUV("exor"); DUV.A(ASig); DUV.B(BSig); DUV.F(FSig); sc_start(); // run forever return 0; } REF:Introduction to SystemC by DeianTabakov Rice University Houston, TX

  18. Simulation in Terminal REF:Introduction to SystemC by DeianTabakov Rice University Houston, TX

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