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Computer Organization Lecture 10

Computer Organization Lecture 10. Exam 1 results Project 3: program counter R-type control. Exam 1. Problem 10. Reset asynchronous to clock and overrides it Flip-flops only change on rising edge of clock Data at D input transferred to FF each clock. Problem 10 solution. Sin always H

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Computer Organization Lecture 10

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  1. Computer OrganizationLecture 10 Exam 1 results Project 3: program counter R-type control University of Portland School of Engineering

  2. Exam 1 University of Portland School of Engineering

  3. Problem 10 Reset asynchronous to clock and overrides it Flip-flops only change on rising edge of clock Data at D input transferred to FF each clock University of Portland School of Engineering

  4. Problem 10 solution • Sin always H • Q3 input always H • Q2 input = Q3 • Q1 input L when (Sin and Q3) both H • Q0 input H when (Q2 and Q3) both L University of Portland School of Engineering

  5. Problem 10 state table University of Portland School of Engineering

  6. Project 3 overview Design a 16-bit, writable program counter University of Portland School of Engineering

  7. Reset Clock PCinc PCwr PC PCin Project 3 block diagram University of Portland School of Engineering

  8. ck2 ck3 ck1 ck4 ck5 Datapath and controller Controller Input University of Portland School of Engineering

  9. Instruction fetch Execution Register write Instruction decode, register read Memory access Datapath timing 1 2 3 4 5 Timing similar to shift register University of Portland School of Engineering

  10. Instruction fetch Clock 1 • Operations • IR = memory[PC] • PC = PC + 4 • Functional units • PC addresses memory • Memory read, then written to IR • PC address sent to ALU and incremented by 4 • PC+4 written (unconditional) University of Portland School of Engineering

  11. 00 Determine control for IF Clock 1 University of Portland School of Engineering

  12. Inst decode & reg read Clock 2 • Operations • A = Reg [IR(25-21)] • B = Reg [IR(20-16)] • ALUout = PC + (sign-extend( IR(15-0))<<2) • Functional units • Reg file read and clocked into A, B • ALU determines branch address, ALUout clocked University of Portland School of Engineering

  13. 00 Determine control for ID Clock 2 Optimistic branch address University of Portland School of Engineering

  14. Execution Clock 3 Opcode determines instruction type • R-Type ALUout = A funct B • Memory reference ALUout = A + sign-extend (IR[15-0]) • Branch If (A == B), PC = ALUout • Jump PC = PC[31-18] || (IR[25-0]<<2) University of Portland School of Engineering

  15. Control for R-type EX? Clock 3 University of Portland School of Engineering

  16. R-type register write Clock 4 • Operation • Reg [ IR(15-11)] = ALUout • Functional units • ALUout contains result data • Data written to Reg file We often call this write-back or WB University of Portland School of Engineering

  17. Control for R-type WB? Clock 4 University of Portland School of Engineering

  18. 00 00 10 Complete R-type University of Portland School of Engineering

  19. R-type instruction timing Clock Function Register Write Instruction Fetch Instruction Fetch Decode, Reg Read University of Portland School of Engineering

  20. University of Portland School of Engineering

  21. 10 Control for R-type EX? Clock 3 University of Portland School of Engineering

  22. Control for R-type WB? Clock 4 University of Portland School of Engineering

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