Network Topologies

1. Network Topologies • Topology – how nodes are connected – where there is a wire between 2 nodes. • Routing – the path a message takes to get from one node to another. • Network connections can be static or dynamic (ex. Bus)

2. Network Properties • Diameter – Maximum distance between nodes • Degree – maximum number of connections on a node • Bisection Bandwidth – minimum number of edges that when removed divide the nodes into two equal sized mutually exclusive sets • Node and edge connectivity – the number of nodes or edges that must fail in order to disconnect the network.

3. Big or Small, what do you want

4. Direct Interconnections • Complete – every node directly connected to every other node • Linear array – each node connected to just the next node • Ring – linear except last connected to first • d-dimensional mesh – generally each dimension is the same size so number of nodes = kd • d-dimensional torus – mesh with ends connected to the first.

5. Hypercube • The number of nodes is a power of 2 (n=2k) • Look at the node number as a k-bit binary value • Node p is connected to the k nodes where the bit pattern in connected nodes differ from the bit pattern for p by one bit being different.

6. Complete Binary Tree • Has n=2k-1 nodes • Internal nodes have degree 3 • Arranged like a binary tree

7. Topology Properties

8. Embeddings • The process of finding a mapping from one topology into another. • If many topologies can be easily mapped onto another topology then that topology is very versatile in that programmers can write their algorithm with one topology in mind (the easiest for the algorithm), but have it actually implemented on another toplogy

9. Ring to Hypercube Embedding • Assume the ring has a power of 2 nodes • Find a sequence of hypercube nodes where adjacent items in the sequence are connected in the hypercube. • Method – start with the sequence (0,1). • Create two new sequences, one being the original sequence with 0 concatenated to the front and the other with 1 concatenated to the front. • Reverse the second sequence • Concatenate the two sequences • Repeat as needed.

10. 2D Mesh to Hypercube Embedding • Look at a n1 x n2 mesh with n total nodes (also n=2k) • Look at the ring sequence for a ring of size n1 (a) and a sequence of size n2 (b). • Map A(i,j) as aibj.

11. Dynamic Interconnection Networks • Bus Networks • Every node connected to a common bus • Only one pair can communicate at one time • Limited scalability • Crossbar switch • Viewed as an n x n arrangement of switches • Also limited scalability O(n2) switches

12. More Dynamic Networks • Omega – uses many 2-input, 2-output switches. Each switch can pass through, crossover, first input is both outputs, second input is both outputs • n x n network has (log n) stages where each stage has n/2 switches. • Node a is connected to 2 nodes b and c where • b = cyclic left shift one bit of the binary value of a • c = b with right bit inverted. • Message travels through log n switches

13. Butterfly Network • Node a is connected to nodes b and c where • b is the same as a • c differs from a by the ith bit from the left (i is the stage). • Again log n time to go through the switches • Each stage has n switches • Total number of switches n log n

14. Baseline • Node a is connected nodes b and c where • b is a cyclic right shift of the k-i last bits of a • k is the number of bits in the representation of the node • i is the stage number • c is the rightmost bit of a inverted then a right cyclic shift of the k-i last bits. • Again time O(log n) and HW costs O(n log n)

15. Skimming • Just skim the routing, switching and Flow Control sections. They are covered in a networks course. • This is more HW than we need in our course which will focus on the SW and algorithms.

16. Cache Memory • Faster to get values from cache than main memory (20-200 times slower). • Spatial locality • Will use memory soon close to current memory address • Fetch from main into cache in blocks (faster than one at a time • Temporal locality • Will reuse this memory location soon. • Will not have to wait for that memory to be loaded into cache if it is still there

17. Mapping Methods • Just skim. Covered in detail in 311. • Not significant for our perspective.

18. Replacement Policies • When cache is full and we need a memory location that is not in cache, a piece of cache must be overwritten • LRU • LFU • Random

19. Memory Writes and Cache • The processor writes to cache, not to main memory. So, when is main memory changed? • Write Through • When changing a piece of cache, start the write of that memory to main memory. • Since takes a long time, it proceeds independently of processor. • So, have a write buffer.

20. Write Back • Only write to main memory when overwriting that part of cache • Use a “dirty” bit to indicate that block of cache has a changed location in it. • When overwriting that cache block, if it is not dirty, do not have to write the block to main memory, but if it is dirty, then write to main memory.

21. Cache Coherency • If you have shared memory among several processors (cores) and each processor has a local cache, then memory contents and cache may not agree if some processor has written to cache.

22. Snooping Protocols • Assumes memory access is done using a common memory bus. The bus must contain the address as well as the data. • When using write through, every cache controller is listening to the bus. • When it “hears” a write to an address it also has in its cache, it also copies the written value and updates its cache copy of that memory location

23. Directory Based Coherence • Used if there is no common memory bus • Sharing distributed memory • Each memory unit has a directory of which blocks of main memory are being used by other processors cache