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LEAT

LEAT. Alain Giulieri, Fabrice Muller LEAT – UMR 6071 Polytech’Nice - Sophia. LEAT. Laboratoire d'Electronique, Antennes et Télécommunications MODELISATION, CONCEPTION SYSTEME D'OBJETS COMMUNICANTS (Michel Auguin) Validation des spécifications au niveau système

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LEAT

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  1. LEAT Alain Giulieri, Fabrice Muller LEAT – UMR 6071 Polytech’Nice - Sophia

  2. LEAT • Laboratoire d'Electronique, Antennes et Télécommunications • MODELISATION, CONCEPTION SYSTEME D'OBJETS COMMUNICANTS (Michel Auguin) • Validation des spécifications au niveau système • Modélisation, optimisation de la consommation • Modélisation comportementale • Conception microélectronique RF, SOC, SIP • ANTENNES INTEGREES ET ANTENNES ACTIVES • MODELISATION ELECTROMAGNETIQUE, OPTIMISATION ET PROBLEMES INVERSES • ANTENNES DIRECTIVES, SYSTEMES DE DETECTION ET D'IMAGERIE MICROONDE ET MILLIMETRIQUE • environ 32 permanents et 34 non permanents

  3. Work-in-progress in LEAT Lab.Hardware RTOS • Designing of a Full Hardware RTOS • Multiprocessor • Services • creation / deletion of a task service • priority policies, user-defined policies • online scheduling service • task delay service • lock / unlock services • suspend / resume services • semaphore services • message services (work in progress) • Generic (static) • Number of Processors • Maximum of tasks per processor • Number of Semaphores

  4. Work-in-progress in LEAT Lab.Related Works on Hw RTOS : Granularity ? Fine-grained Granularity Coarse-grained Granularity RTOS Atalanta [43] developed by Vincent J. MOONEY Our solution System Level (SystemC) HDL Level HDL Level Design ONLY Top Down Approach Optimization of Architecture (cache) More configurations

  5. Work-in-progress in LEAT Lab.Objectives processor 0 processor 1 Task 1,4,5 Task 2,3 Application Layer IRQ Handler Services IRQ Handler Services Sw RTOS Layer event + status + values event + status + values parameters + command parameters + command HW RTOS Module • Multiprocessor support with • Local scheduling • Global scheduling • Modify policies at run time • By the user (Service) • By the Self-Adaptation Manager • Hardware task scheduling • Scheduling of mixed Hw/Sw tasks Example of 2 processors

  6. Work-in-progress in LEAT Lab.1 : Multiprocessor Approach Scheduler_Manager scheduler_bus Sw Hw priority scheduling policies state of tasks … Service X memories or registers Scheduler_Controller External Bus rechedule event Semaphore Proc N Read Parameters Algorithms_Manager Delay RM EDF Proc 1 Interface Global Scheduling User Scheduling Proc 0 Next_Task_Manager irq new task(s) elected

  7. Work-in-progress in LEAT Lab.2 : Modification of the Scheduling Policy SchedulingPolicySet(int processorId, int local_global, int type) ProcessorId GlobalLocal type of scheduling field RM EDF USER_SCHEDULING … rechedule Interface Scheduler Controller Algorithms Manager Interface Proc 0 elected task(s) Proc 0 Self-Adaptation Manager priority scheduling policies state of tasks … Proc 0 Proc 0

  8. Work-in-progress in LEAT Lab.3: Hardware Task Scheduling • Integrated a new scheduling algorithms for Hw/Sw tasks • Placer Manager • Sw services • Management of Hw reconfiguration • Interaction with the Scheduler manager • Dedicated interface in order to reduce overhead • ICAP control (for Xilinx) • Example User (Sw Services) Placer Manager Sw ICAP Proc. T2 Proc. Scheduler Controller Proc. T0 T1 Hw Area Hw Task

  9. Work-in-progress in LEAT Lab.Results : Area & Performances Worst Case Latency Time : WCLTtask_delay = 4 + Processor_Number x (Task_Number + 4) in cycles Technology : Virtex II Pro Tools : Precision Synthesis 2007, ISE 9.1i 16 tasks, F=70MHz ALT (Average Latency Time) = 307 ns for each processor at the same time

  10. Work-in-progress in LEAT Lab.Experimentation on ML310 Board 32Kb instruction 32Kb data 32Kb instruction 32Kb data Local memory Local memory Processor 0 PPC Processor 1 PPC PLB Bus (100MHz) Bridge HwRTOS Shared memory 128K bytes OPB Bus UART VirtexII Pro 8 tasks per processor management of 2 processors 8 semaphores

  11. Work-in-progress in LEAT Lab.Results : Software & Debug select windows display reconfiguration save/load trace task_id_type idT2; void T2() { int priority; status_type status; int cpt = 0; while (1) { status = taskPriorityGet(idT2, &priority); /* Task Delay */ rtos_printf("P0> %d Task T2 (%d, %d) \r\n", cpt, idT2, priority); status = taskDelay(idT2, 300000); // (10 µs = 1 tick) if (cpt == 7) { rtos_printf("P0> Exit & Delete Task 2 \r\n"); break; } else cpt++; } } int main(void) { status_type status; /* Init Hw RTOS */ init(); /* Task Spawn : Task 2 */ rtos_printf("P0> Create Task 2 \r\n"); status = taskSpawn(&idT2, "T2", T2, 40); /* Create Shared Mutex Semaphore for RS232 */ rtos_printf("#0> Create Mutex Semaphore \r\n"); status = sem_MCreate(&semMutexRS232, "Display Mutex"); /* Start RTOS */ rtos_printf("RUN RTOS ...\r\n"); start(); return 0; } serial / TCP VxWork-like Primitive

  12. Work-in-progress in LEAT Lab.Actual & Future Works • Hw RTOS • Partial Reconfiguration services • Global scheduling, Hw/Sw scheduling for HRT/SRT • Message services • Hw Debug Manager • Scheduling • Local Scheduling • Mixed HRT & SRT (best processor utilization) • Real Urgency First Scheduling Algorithm: RUF • Algorithms for AETHER Projet (Scheduling of Hw Task) • Mixed Global & Local Scheduling • HRT possible (Sw Task version) • Migration to Virtex5

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