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The LAV primitive generator

The LAV primitive generator. Francesco Gonnella 18 th December 2013 TDAQ Working Group Meeting. LAV trigger generator inside PP. OBTRIG. TRIG. TRIGGEN. Input data is read from the OBTRIG fifo ; Data is elaborated from TRIGGEN module Output data is written to TRIG fifo.

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The LAV primitive generator

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  1. The LAV primitive generator Francesco Gonnella 18thDecember 2013 TDAQ Working Group Meeting Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  2. LAV trigger generator inside PP OBTRIG TRIG TRIGGEN • Input data is read from the OBTRIG fifo; • Data is elaborated from TRIGGEN module • Output data is written to TRIG fifo Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  3. LAV front-end electronics LAV electronics channel working principle To TDC To TDC • Split the input signal into two copies: 1 copy to comparator + 1 copy to analog sums • Clamp the signal preserving its width, wide dynamical range is expected (MIP 70 MeV ~ 10 mV, high energy γ ~ 1V) • Amplify the signal and compare with 2 thresholds • Each threshold is independently adjustable up to 250 mV • Produce an LVDS signal and send the signal to the digital read out board toanalogsum LVDS Amp 6x Split Low threshold Compare Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy LVDS Clamp Highthreshold Charge reconstruction algorithm The actual dependence of Q on ToT can be obtained using a fit to the distribution of Q vs. ToT. This relation is in principle the same for all the LAV PMTs. The sensitivity of the method is reduced at high charge due to the exponential dependence of Q on ToT. Charge reconstruction in NA62 LAV • Measure ToT vs. charge using QDC and TDC • only during calibration not during experiment • Fit the function Q(ToT) (i.e. polynomial function) • During data taking, measure the time using a TDC only CANopen IN OUT VME custom power 32ch OUT LVDS 16ch IN Analog 32ch OUT LVDS 16ch IN Analog

  4. LAV PP firmware • Physical event reconstruction and and slewing correction • Constant time offset for each channel (cable and time of flight) • Event reconstruction (High and Low High Threshold matching) • Slewing correction • Recognize the end of the 6.4 μs frame (EoF) • Deliver data (primitives and EoF) to SL on a 32-bit bus • Error on FIFO L/H full End-of-Frame signal FIFO L FIFO H Data formatter & threshold retriever FIFO L Slewing calculator Input Stage Offset and map Ch. Selector Event Finder Output stage to TRIG fifo OB FIFO FIFO H FIFO L FIFO H map RAM (ECS) offset RAM (ECS) threshold RAM (ECS) 64 blocks (128 FIFOs) Francesco Gonnella - I.N.F.N. - LaboratoriNazionali di Frascati - Italy

  5. Time-offset corrector module • Receives input stream • Checks if data is a time • Retrieves the proper offset value from offset RAM • Adds the offset to the time • If data is a timestamp (0xA) or a counter (0xB) • Transmits data untouched • Input-output delay:4clock cycles. Time-offset adder clock Data in Data out Data Ready in Data Ready Out address Read enable offset ECS address Offset RAM 13-bit words LSB=100ps Write enable offset Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  6. Channel mapping module Channel mapper • Receives input stream • If data is a time • Reads original channel number • Replaces it with new ch number read from RAM • One bit is used to enable and disable the channel • If data is a timestamp (0xA) or a counter (0xB) • Transmits data untouched • Input-output delay:4clock cycles. clock Data in Data out Data Ready in Data Ready Out ECS Ch. number Read enable address Address (old ch) Mapping RAM 8-bit words (7 = disabled, 6-0 channel number) Write enable Channel Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  7. Channel-selecting module • Redirect fine time to the proper channelfifo • time stamps are sent to all channels at once • Reduce data size form 32 bits to 22 bits FIFO High FIFO Low FIFO High Channel selector clock Write enable FIFO Low Data Ready in Data in FIFO High FIFO Low data bus Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  8. Channel time fifo module • Properly merge time stamp and fine time • Different High and Low FIFO depth: 8 and 16 words • Different High and Low FIFO FSM logic Time Stamp 40-bit data Empty MegaWizard Fifo (8H/16L words) TS: 00112345 Data: 00112348 Data: 00112347 Data: 00112346 TS: 00112344 Data: 00112345 … Output FSM 22-bit data Fine Time Push Fifo Ready Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  9. Event-finder module architecture FIFO High • Event Finder FSM • Wait for High • Look for Low in time • if L is preceding discard it; • If L is successive discard L and H • If L matches H produce output data:block number (6 bit)absolute time (40 bit)rise time (8 bit) FIFO Low FIFO High 2x 32-bit data FIFO Low Block number encoder FIFO High FIFO Low data bus This module works under the assumption that data, for a given channel, are time ordered. Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  10. Threshold retriever module • Parse 2x 32-bit input words: • Retrieve proper threshold values from RAM • Produce a formatted 72-bit word: • Need to know thresholds form DCS. • Not yet done Data formatter & Thresholdretriever clock 72-bit Data out 32-bit Data in Strobe in Strobe out address Read enable offset ECS address Threshold RAM Thr WE Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  11. High Level Synthesis Calculator • Module realised using High Level Synthesis (A. Bellotta) • HLS calculator performing slewing calculation: • Working frequency: 160 MHz • Input-output latency: 9 clk • Throughput: 1 clk • Reasonable resources utilization HLS Slewing correction calculator clock 72-bit Data in 40-bit data out Strobe in Strobe out Megawizard divider: Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  12. LAV-PP output data format • Data sent from each PP to SL is formatted as following: • Data is composed of 2 32-bit words, the first starting with “10” • The End of Frame is 1 word starting with “11” • For example: Reminder: 0xC = ‘1100’ Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  13. PP FPGA: resources utilization +---------------------------------------------------------------------------+ ; Fitter Summary ; +-------------------------------+-------------------------------------------+ ; Fitter Status ; Successful - Tue Nov 19 11:56:52 2013 ; ; Quartus II 64-Bit Version ; 12.0 Build 178 05/31/2012 SJ Full Version ; ; Revision Name ; pp_fpga ; ; Top-level Entity Name ; pp_fpga ; ; Family ; Stratix III ; ; Device ; EP3SL110F1152C4 ; ; Timing Models ; Final ; ; Logicutilization ; 74 % ; ; Combinational ALUTs ; 39,996 / 86,000 ( 47 % ) ; ; Memory ALUTs ; 3,268 / 43,000 ( 8 % ) ; ; Dedicatedlogicregisters ; 43,150 / 86,000 ( 50 % ) ; ; Total registers ; 43806 ; ; Total pins ; 581 / 744 ( 78 % ) ; ; Total virtualpins ; 0 ; ; Total block memorybits ; 3,276,930 / 4,303,872 ( 76 % ) ; ; DSP block 18-bit elements ; 4 / 288 ( 1 % ) ; ; Total PLLs ; 3 / 8 ( 38 % ) ; ; Total DLLs ; 1 / 4 ( 25 % ) ; +-------------------------------+-------------------------------------------+ Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  14. LAV SL firmware • Primitive merging and Multiple Trigger Packet (MTP) generation • Merge physical hit times from the 4 PPs • Group together hits within a given cluster (5 ns window) • Evaluate the average of the clusters, obtaining primitive times • Sort primitive times • Produce an MTP • Error on primitive lost Cluster hit number PP0 FIFO Sorting module Data counter PP1 FIFO Average calculator Output stage Clustering module Data merger FIFO sorting RAM PP2 FIFO PP3 FIFO Francesco Gonnella - I.N.F.N. - LaboratoriNazionali di Frascati - Italy

  15. Data Merger • FSM handling the 4 FIFOs • Priority switches cyclically among the 4 FIFOs • FSM waits for EoF words from all the enabled PPs before producing a global EoF word EoF 2300 2345 2356 32 bit EoF 2322 Data merger EoF 2300 2331 2345 2358 2322 2356 32 bit 32 bit EoF 2331 2358 32 bit EoF 32 bit Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  16. Clustering module • Composed of 32 (can be increased) basic cells • Each cell stores the first Time received • If successive times match Time it adds them to Sum and increases Number.If not, it sends the time to the next cell • The matching window is asymmetrically programmable (up to ±12.5 ns) through 2 independent registers • At the EoF it acts as a shift register, giving as output all the cluster times and number of events per cluster • The Average Calculator performs the division between Sum and Number • Number is also fed to the sorting module to be written into the final primitive data • Clustering cell • Time • Number • Sum Time in Time out Number in Number out Sum in Sum out Low limit register High limit register • 160 MHz • Latency : 3 clk • Throughput: 1 clk HLS Average calculator (A. Bellotta) Clustering cell Clustering cell Clustering cell Clustering cell Number out Sum out Average out This is a simplified scheme: actually time values are split into Coarse and Fine so that divisions are performed on 8-bit values rather than 40-bit. Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  17. Sorting module and RAM • Composed of 32 (can be increased) basic cells • Each cell receives a time. The first time is stored. • Successive times: • If greater than the stored time simply pass through the cell • If smaller pass through the cell increasing the position of the cell • At the EoF, it acts as a shift register giving as output all the times and their respective positions • Data is fed into a RAM and addressed with their position • In the meantime the number of primitives is counted out • At the and the sorting RAM is read out starting from address 0 up to the last counted datum • Sorting cell • Time • Position Time in Time out Position in Position out From clustering module Number of hits Sorting cell Sortingcell RAM Sorting cell Data Address Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  18. LAV-SL output data format • Data sent from SL is formatted as following: • Data is composed of 3 32-bit words, to fit global firmware specs • For example: Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  19. SL FPGA: resources utilization +---------------------------------------------------------------------------+ ; Fitter Summary ; +-------------------------------+-------------------------------------------+ ; Fitter Status ; Successful - Thu Nov 28 12:59:38 2013 ; ; Quartus II 64-Bit Version ; 12.0 Build 178 05/31/2012 SJ Full Version ; ; Revision Name ; sl_fpga ; ; Top-level Entity Name ; sl_fpga ; ; Family ; Stratix III ; ; Device ; EP3SL110F1152C4 ; ; Timing Models ; Final ; ; Logicutilization ; 39 % ; ; Combinational ALUTs ; 22,484 / 86,000 ( 26 % ) ; ; Memory ALUTs ; 257 / 43,000 ( < 1 % ) ; ; Dedicatedlogicregisters ; 18,758 / 86,000 ( 22 % ) ; ; Total registers ; 18898 ; ; Total pins ; 728 / 744 ( 98 % ) ; ; Total virtualpins ; 0 ; ; Total block memorybits ; 1,450,850 / 4,303,872 ( 34 % ) ; ; DSP block 18-bit elements ; 0 / 288 ( 0 % ) ; ; Total PLLs ; 2 / 8 ( 25 % ) ; ; Total DLLs ; 0 / 4 ( 0 % ) ; +-------------------------------+-------------------------------------------+ Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  20. Conclusions • LAV primitive generator has been successfully integrated with the new version 2 TEL62 firmware • LAV primitive generator has been tested successfully during last dry run, results will be/have been presented by R. Piandani • Resources are reasonable for SL (~40%), at the limit for PP (74%) • Possible improvements • Some internal FIFO (especially in the PP) could be made available from ECS for debug proposes • Introduce the possibility or sending/not sending the primitive on the basis of the number of hits of the cluster • The “rise time” information is available at SL level so a preliminary charge reconstruction procedure is under study • Requests: • We are performing very interesting tests with cosmic rays using periodic triggers. Could it be possible to use LAV fw to generate triggers? This would tremendously improve our efficiency. Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy

  21. Thank you for your attention francesco.gonnella@lnf.infn.it

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