Optimizations and Tradeoffs

1. 20 16 transistors 4 transistors w F1 2 gate-delays 1 gate-delay 15 x y w e ors) size (transistors) t 10 z F1 F2 x w 5 x r F2 y (t 1 2 3 4 F1 = wxy + wxy’ F2 = wx delay (gate-delays) (a) (b) (c) Optimizations and Tradeoffs • We now know how to build digital circuits • How can we build better circuits? • Let’s consider two important design criteria • Delay – the time from inputs changing to new correct stable output • Size – the number of transistors • For quick estimation, assume • Every gate has delay of “1 gate-delay” • Every gate input requires 2 transistors • Ignore inverters Transforming F1 to F2 represents an optimization: Better in all criteria of interest si = wx(y+y’) = wx

2. 20 14 transistors 12 transistors w 2 gate-delays 3 gate-delays w 15 G1 x G2 x 10 G2 G1 y w 5 z y z 1 2 3 4 G1 = wx + wy + z G2 = w(x+y) + z delay (gate-delays) Optimizations and Tradeoffs • Tradeoff • Improves some, but worsens other, criteria of interest Transforming G1 to G2 represents a tradeoff: Some criteria better, others worse. size (transistors) e z

3. e e z z del a y del a y Optimizations and Tradeoffs Tradeoffs • We obviously prefer optimizations, but often must accept tradeoffs • You can’t build a car that is the most comfortable, and has the best fuel efficiency, and is the fastest – you have to give up something to gain other things. Optimizations Some criteria of interest are improved, while others are worsened All criteria of interest are improved (or at least kept the same) size size si si si ansis e z

4. 0 0 x m m y y’ x’ F n n x’ F y’ n y’ n m x’ 0 1 1 y x m y x 1 Combinational Logic Optimization and Tradeoffs Example • Two-level size optimization using algebraic methods • Goal: circuit with only two levels (ORed AND gates), with minimum transistors • Though transistors getting cheaper (Moore’s Law), they still cost something • Define problem algebraically • Sum-of-products yields two levels • F = abc + abc’ is sum-of-products; G = w(xy + z) is not. • Transform sum-of-products equation to have fewest literals and terms • Each literal and term translates to a gate input, each of which translates to about 2 transistors (see Ch. 2) • Ignore inverters for simplicity F = xyz + xyz’ + x’y’z’ + x’y’z F = xy(z + z’) + x’y’(z + z’) F = xy*1 + x’y’*1 F = xy + x’y’ 4 literals + 2 terms = 6 gate inputs 6 gate inputs = 12 transistors Note: Assuming 4-transistor 2-input AND/OR circuits; in reality, only NAND/NOR are so efficient.

5. Algebraic Two-Level Size Minimization • Previous example showed common algebraic minimization method • (Multiply out to sum-of-products, then) • Apply following as much possible • ab + ab’ = a(b + b’) = a*1 = a • “Combining terms to eliminate a variable” • (Formally called the “Uniting theorem”) • Duplicating a term sometimes helps • Note that doesn’t change function • c + d = c + d + d = c + d + d + d + d ... • Sometimes after combining terms, can combine resulting terms F = xyz + xyz’ + x’y’z’ + x’y’z F = xy(z + z’) + x’y’(z + z’) F = xy*1 + x’y’*1 F = xy + x’y’ a F = x’y’z’ + x’y’z + x’yz F = x’y’z’ + x’y’z + x’y’z + x’yz F = x’y’(z+z’) + x’z(y’+y) F = x’y’ + x’z a G = xy’z’ + xy’z + xyz + xyz’ G = xy’(z’+z) + xy(z+z’) G = xy’ + xy (now do again) G = x(y’+y) G = x a

6. x’yz x’yz’ x’y’z xyz’ xy’z’ xy’z xyz Treat left & right as adjacent too F yz x 00 01 11 10 0 1 1 0 0 1 0 0 1 1 yz F x 00 01 11 10 0 1 1 0 0 1 0 0 1 1 x ’ y ’ x y F = xyz + xyz’ + x’y’z’ + x’y’z F = xy(z + z’) + x’y’(z + z’) F = xy*1 + x’y’*1 F = xy + x’y’ Easier than all that algebra: Karnaugh Maps for Two-Level Size Minimization yz F Notice not in binary order • Easy to miss “seeing” possible opportunities to combine terms • Karnaugh Maps (K-maps) • Graphical method to help us find opportunities to combine terms • Minterms differing in one variable are adjacent in the map • Can clearly see opportunities to combine terms – look for adjacent 1s • For F, clearly two opportunities • Top left circle is shorthand for x’y’z’+x’y’z = x’y’(z’+z) = x’y’(1) = x’y’ • Draw circle, write term that has all the literals except the one that changes in the circle • Circle xy, x=1 & y=1 in both cells of the circle, but z changes (z=1 in one cell, 0 in the other) • Minimized function: OR the final terms x 00 01 11 10 K-map 0 x’y’z’ a 1 F = x’y’z + xyz + xyz’ + x’y’z’ a a F = x’y’ + xy

7. K-maps • Four adjacent 1s means two variables can be eliminated • Makes intuitive sense – those two variables appear in all combinations, so one must be true • Draw one big circle – shorthand for the algebraic transformations above G = xy’z’ + xy’z + xyz + xyz’ G = x(y’z’+ y’z + yz + yz’) (must be true) G = x(y’(z’+z) + y(z+z’)) G = x(y’+y) G = x Draw the biggest circle possible, or you’ll have more terms than really needed

8. H = x’y’z + x’yz + xy’z + xyz (xy appears in all combinations) I yz y ’ z x 00 01 11 10 0 0 1 0 0 1 1 1 1 1 x The two circles are shorthand for: I = x’y’z + xy’z’ + xy’z + xyz + xyz’ I = x’y’z + xy’z + xy’z’ + xy’z + xyz + xyz’ I = (x’y’z + xy’z) + (xy’z’ + xy’z + xyz + xyz’) I = (y’z) + (x) K-maps • Four adjacent cells can be in shape of a square • OK to cover a 1 twice • Just like duplicating a term • Remember, c + d = c + d + d • No need to cover 1s more than once • Yields extra terms – not minimized a a a

9. K-maps • Circles can cross left/right sides • Remember, edges are adjacent • Minterms differ in one variable only • Circles must have 1, 2, 4, or 8 cells – 3, 5, or 7 not allowed • 3/5/7 doesn’t correspond to algebraic transformations that combine terms to eliminate a variable • Circling all the cells is OK • Function just equals 1

10. z F y 0 1 0 1 K-maps for Four Variables • Four-variable K-map follows same principle • Adjacent cells differ in one variable • Left/right adjacent • Top/bottom also adjacent • 5 and 6 variable maps exist • But hard to use • Two-variable maps exist • But not very useful – easy to do algebraically by hand F=w’xy’+yz G=z

11. G bc’ bc a 00 01 11 10 a’b’c’ 0 1 0 0 1 1 1 1 1 1 a G bc a c ’ 00 01 11 10 0 1 0 0 1 1 1 1 1 1 a Two-Level Size Minimization Using K-maps • Example: Minimize: • G = a + a’b’c’ + b*(c’ + bc’) • 1. Convert to sum-of-products • G = a + a’b’c’ + bc’ + bc’ • 2. Place 1s in appropriate cells General K-map method • Convert the function’s equation into sum-of-products form • Place 1s in the appropriate K-map cells for each term • Cover all 1s by drawing the fewest largest circles, with every 1 included at least once; write the corresponding term for each circle • OR all the resulting terms to create the minimized function. a • 3. Cover 1s • 4. OR terms: G = a + c’

12. a’b’c’d’ a’b’cd’ ab’c’d’ a’bd a’bcd’ ab’cd’ b ’ d ’ 0 0 a ’ bc 0 1 1 a ’ bd 0 0 0 0 0 0 Funny-looking circle, but remember that left/right adjacent, and top/bottom adjacent H = b’d’ + a’bc + a’bd Two-Level Size Minimization Using K-maps – Four Variable Example • Minimize: • H = a’b’(cd’ + c’d’) + ab’c’d’ + ab’cd’ + a’bd + a’bcd’ 1. Convert to sum-of-products: • H = a’b’cd’ + a’b’c’d’ + ab’c’d’ + ab’cd’ + a’bd + a’bcd’ 2. Place 1s in K-map cells 3. Cover 1s 4. OR resulting terms H c d ab 00 01 11 10 00 1 1 a 01 1 11 10 1 1

13. 22 transistors a 2 gate delays 4 a F2 4 F1 b b 20 4 ) F2 15 a c ors c 4 6 t e z 10 d si 6 F1 d ansis r 5 4 4 (t a e 16 transistors c 6 4 gate-delays e 1 2 3 4 delay (gate-delays) F1 = ab + acd + ace F2 = a(b+c(d+e)) (a) (b) (c) Multi-Level Logic Optimization – Performance/Size Tradeoffs • We don’t always need the speed of two level logic • Multiple levels may yield fewer gates • Example • F1 = ab + acd + ace  F2 = ab + ac(d + e) = a(b + c(d + e)) • General technique: Factor out literals – xy + xz = x(y+z) size (transistors)

14. A: abcd + abcef = abc(d + ef) • Has fewer gate inputs, thus fewer transistors 22 transistors 18 transistors F1 2 gate delays 3 gate delays 20 F2 a a ) 6 15 b b size (transistors) 8 4 c c F2 d 10 d 4 F1 4 a 5 e b c 4 10 e 1 2 3 4 f f delay (gate-delays) F1 = abcd + abcef F2 = abc(d + ef) (a) (b) (c) Multi-Level Example • Q: Use multiple levels to reduce number of transistors for • F1 = abcd + abcef a

15. Inputs: x; Outputs: y x y x’ x x’ x’ x x’ x x’ if x = 1,1,0,0 x x’ x x then y = 0,1,1,0,0 S0 S1 S2 S3 S0 S1 y=0 y=1 y=0 y=1 y=0 y=1 S0 S0 S1 S1 S1 S1 S0 S2 S2 S0 For the same sequence of inputs, the output of the two FSMs is the same State Reduction (State Minimization) • Goal: Reduce number of states in FSM without changing behavior • Fewer states potentially reduces size of state register • Consider the two FSMs below with x=1, then 1, then 0, 0 a state state x x y y

16. Inputs: x; Outputs: y States S0 and S2 equivalent States S1 and S3 equivalent x’ x x’ x x’ x x’ x S0 S1 S2 S3 y=0 y=0 y=1 y=1 x’ x x’ x S0, S2 S1, S3 y=0 y=1 State Reduction: Equivalent States Two states are equivalent if: 1. They assign the same values to outputs • e.g. S0 and S2 both assign y to 0, • S1 and S3 both assign y to 1 2. AND, for all possible sequences of inputs, the FSM outputs will be the same starting from either state • e.g. say x=1,1,0,0,… • starting from S1, y=1,1,0,0,… • starting from S3, y=1,1,0,0,… a

17. Inputs: x; Outputs: y x’ Start from S1, x=0 x’ x x’ x x’ x x’ x S0 S1 S2 S3 x’ x x’ x y=0 y=1 y=1 y=1 x x’ x S0 S1 S2 S3 y=0 y=1 y=1 y=1 Start from S3, x=0 x’ x’ x x’ x x x’ x S0 S1 S2 S3 y=0 y=1 y=1 y=1 State Reduction: Example with no Equivalencies • Another example… • State S0 is not equivalent with any other state since its output (y=0) differs from other states’ output • Consider state S1 and S3 a • Outputs are initially the same (y=1) • From S1, when x=0, go to S2 where y=1 • From S3, when x=0, go to S0 where y=0 • Outputs differ, so S1 and S3 are not equivalent.

18. Inputs: b; Outputs: x x=0 00 b’ Off b x=1 x=1 x=1 11 10 01 10 11 On1 On2 On3 1 1 1 1 0 0 0 0 State Encoding • Encoding: Assigning a unique bit representation to each state • Different encodings may optimize size, or tradeoff size and performance • Consider 3-Cycle Laser Timer… • Example 3.7’s encoding: 15 gate inputs • Try alternative encoding • x = s1 + s0 • n1 = s0 • n0 = s1’b + s1’s0 • Only 8 gate inputs a

19. One-hot encoding One bit per state – a bit being ‘1’ corresponds to a particular state Alternative to minimum bit-width encoding in previous example For A, B, C, D: A: 0001, B: 0010, C: 0100, D: 1000 Example: FSM that outputs 0, 1, 1, 1 Equations if one-hot encoding: n3 = s2; n2 = s1; n1 = s0; x = s3 + s2 + s1 Fewer gates and only one level of logic – less delay than two levels, so faster clock frequency Inputs: none; Outputs: x x=0 x=1 00 11 A D 0001 1000 B C 01 10 0100 0010 x=1 x=1 x x n1 8 binary 6 s3 s2 s1 s0 n0 s1 s0 4 one-hot clk State register clk State register 2 n0 n1 1 2 3 4 n2 n3 delay (gate-delays) State Encoding: One-Hot Encoding a

20. 0001 0010 0100 1000 One-Hot Encoding Example: Three-Cycles-High Laser Timer • Four states – Use four-bit one-hot encoding • State table leads to equations: • x = s3 + s2 + s1 • n3 = s2 • n2 = s1 • n1 = s0*b • n0 = s0*b’ + s3 • Smaller • 3+0+0+2+(2+2) = 9 gate inputs • Earlier binary encoding (Ch 3): 15 gate inputs • Faster • Critical path: n0 = s0*b’ + s3 • Previously: n0 = s1’s0’b + s1s0’ • 2-input AND slightly faster than 3-input AND Inputs: b; Outputs: x x=0 b’ Off b x=1 x=1 x=1 On1 On2 On3 a