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NAND and NOR Gates

NAND and NOR Gates. ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning. NAND and NOR Gates. DeMorgan's Laws. (X ∙ Y)' = X' + Y'. (X + Y)' = X' ∙ Y'. Functionally Complete Set. Any function can be realized using only NAND gates. SOP to NAND-NAND.

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NAND and NOR Gates

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  1. NAND and NOR Gates ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

  2. NAND and NOR Gates 311_07

  3. DeMorgan's Laws • (X ∙ Y)' = X' + Y' • (X + Y)' = X' ∙ Y' 311_07

  4. Functionally Complete Set • Any function can be realized using only NAND gates 311_07

  5. SOP to NAND-NAND G = WXY + YZ 311_07

  6. MOSFETs NMOS (n-channel) OFF ON PMOS (p-channel) ON OFF 311_07

  7. CMOS Inverter 311_07

  8. CMOS Inverter +V (H = 1) +V (H = 1) ON OFF OFF ON (L = 0) (L = 0) 311_07

  9. CMOS NAND Gate (H = 1) (L = 0) 311_07

  10. CMOS NAND Gate (H = 1) (L = 0) 311_07

  11. CMOS NAND Gate (H = 1) (L = 0) 311_07

  12. CMOS NAND Gate (H = 1) (L = 0) 311_07

  13. CMOS NAND Gate (H = 1) (L = 0) 311_07

  14. CMOS NOR Gate 311_07

  15. VOHmin VIHmin VILmax VOLmax Noise Margin 311_07

  16. Electrical Characteristics NMH = VOHmin - VIHmin = 4.4 V - 3.15 V = 1.25 V NML = VILmax - VOLmax = 1.35 V - 0.1 V = 1.25 V 311_07

  17. Propagation Delay 311_07

  18. Propagation Delay 311_07

  19. Summary • NAND and NOR Gates • DeMorgan's Laws • SOP to NAND-NAND • MOSFETs • CMOS Logic Gates • Inverter, NAND, NOR • Electrical Characteristics • Noise Margin • Propagation Delay 311_07

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