Paper Report

1. Paper Report On the Generation of Functional Test Programs for the Cache Replacement Logic W. J. Perez H. Universidad del Valle Grupode Bionanoelectrónica Cali, Colombia Universidad Pedagógicay Tecnológicade Colombia, GrupoGiraSogamoso, Colombia D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy 2009 Asian Test Symposium Presenter: Jyun-Yan Li

2. Abstract • Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-frequency devices. • While the test of the memory arraywithin the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce.

3. Abstract (cont.) • In this paper we face the issue of generating suitable programs for testing the replacement logic in set-associative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to assess the effectiveness of the method.

4. What is the Problem • IC manufacturing cost most at test and validation processor • Not enough methodology to cope with all testing issue for cache • Cache testing approaches • Hardware based • Usually modifies initial design in order to support testing procedures • Algorithm based • March-like program test data cache • Require special system feature to write/read main memory when the cache is disabled • focusing on testing memory element not cache controller • Software-based Self-Test (SBST) depend on effective test program

5. Related work SBST Data cache Processor Functional test of processor [7] Direct mapped data cache [16] Data controller [8] Determine cache Hit or miss by access cycle which is counter Executing suitable program by ISA instruction and checking the result to detect faults Test cache memory module & control logic A hybrid method for data & instruction controller [9] Determine cache Hit or miss by I-IP which observes response and generates error signal On the Generation of Functional Test Programs for the Cache Replacement Logic This paper:

6. Testing issues-before building FSM • Focus on the data part of cache and replacement mechanism of cache controller • Selecting the effective address of every memory access • Checking expected results is more complex • Not causing produce wrong results, but slowing down its performance • Some mechanism able to verify cache hit or miss as expected • As cache monitor

7. Proposal method • Build FSM of the replacement mechanism • Implementation machine seen as a black box • Observing I/O behavior • Generate a test sequence for testing replacement mechanism • Finding a tour to traverse every edge • generating the sequence of addresses to traverse all the transitions

8. Replacement mechanism modeling • Input I • n address stored in the n ways of cache set • Initial state • Some address produce a cache miss for transfer new state • Output O • Checking hit or miss by the cache monitor • State S • Permutation of n way which way can be replaced • In an n-way set associative, each state has n+1 outgoing transitions • n transitions produce a hit • 1 transition produces a miss

9. Example : 3-way set associative, LRU replacement LRU MRU t1: hit(w1) s0 : w1 w2 w3 t15: hit(w1) t9: miss t7: hit(w2) t8: hit(w3) s4 : w3 w1 w2 s1 : w1 w3 w2 s2 : w2 w1 w3 t19: hit(w1) t10: hit(w2)

10. Replacement mechanism testing • How to generate a transition tours • Chinese Postman Problem (CPP) • Find the shortest tour which every edge is traversed at least once • Using in the undirected graph • Floyd-Warshall algorithm • A sequence of memory accesses that identified the current state indirectly by cache monitor • Back to the original state at the end of sequence • 1. access address (An+1) to remove address An which in the way Wn • 2. read An again that will replaced An-1 (in the Wn-1) and check cache miss/hit • 3.read An-1 again and check miss/hit. Repeat step 3 for all the ways • 4. read n-1 addresses which in the way to cause hit and back to the original state

11. Example : transition tours MRU LRU Initial state 6 A2: hit(w1) s0 : w1 w2 w3 4 A1: miss A2: miss 1 3 A4: miss 2 s4 : w3 w1 w2 s3 : w2 w3 w1 A3: miss A3: hit(w2) 5

12. Example : wrong transition Wrong at the Initial state LRU MRU s2 : w2 w1 w3 error 1 3 A4: miss A2: hit(w2) 2 s1 : w1 w3 w2 s5 : w3 w2 w1 A3: miss

13. How to prove the proposal • How many • instructions in the test program • Clock cycle for the simulation • How much • Fault coverage at the stuck-at fault • Which kind of the faults • Comparing with ? • Compare with March C- in the [16] • Not compare with reference [8] and [9]

14. Experimental result • LEON2 processor with a 3-way data cache • Write through policy • Write no-allocate on a write miss • LRU replacement • Stuck at fault • Cache controller: 26148 • LRU: 11637

15. Conclusion • Present a generic testing method for replacement mechanism of cache controller • Based on the FSM model of circuitry and produce a sequence of memory operation to excite the replacement mechanism • It can be implementation for n-way and any replacement policy • My comment • Another method to verify cache controller • How to select effective address to excite the controller of instruction cache