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  1. Floating-Point Mathematical Co-Processor for a Single-Chip On-Board ComputerTanya Vladimirova, David Eamey, Sven Keller, Prof Sir Martin SweetingSurrey Space CentreUniversity of Surrey, Guildford, Surrey, UK, GU2 7XHTel: +44(0)1483 689278Fax:+44(0)1483 686021email: T.Vladimirova@surrey.ac.uk Page 1

  2. Outline • Introduction • SoC Research at SSC - ChipSat • CORDIC Algorithm • Design of the Co-processor • System-Level Integration • Performance Results • Conclusions Page 2

  3. SOC SoC Research at SSC Surrey Satellite Technology's (SSTL) On-Board Computer (OBC) ChipSat Programme Page 3

  4. CORDIC Algorithm x x x x K1 (x2 + y2)1/2 K1 (x cos z – y sin z) y y y y 0 K1 (y cos z + x sin z) z z z z z + tan-1(y/x) 0 CIRCULAR (m=1),  = sgn z CIRCULAR (m=1),  = - sgn y n -1 K1 =  (1 + 22i)1/2 for n iterations i=0 x x x x 0 x y y y + xz y y 0 z z z z z + y/x 0 LINEAR (m=0),  = sgn z LINEAR (m=0),  = - sgn y x x x x K-1 (x2 - y2)1/2 K1 (x cosh z – y sinh z) y y y y K1 (y cosh z + x sinh z) 0 z z z z z + tanh-1(y/x) 0 HYPERBOLIC (m=-1),  = sgn z HYPERBOLIC (m=-1),  = - sgn y n -1 K-1 =  (1 - 22i)1/2 for n iterations i=0 CORDIC equations CORDIC modes Page 4

  5. Idenitity Domain { sin D if Q mod 4 = 0 } sin(Q 90 + D) = { cos D if Q mod 4 = 1 } { -sin D if Q mod 4 = 2 } { -cos D if Q mod 4 = 3 } |D| < 90 { cos D if Q mod 4 = 0 } cos(Q 90 + D) = { -sin D if Q mod 4 = 1 } { -cos D if Q mod 4 = 2 } { sin D if Q mod 4 = 3 } |D| < 90 tan(Q 90 + D) = sin(Q 90 + D) / cos(Q 90 + D) |D| < 90 tan-1(1/y) = 90 – tan-1 (y) |y| < 1 sinh(Q loge 2 + D) = (2Q/2)[cosh D + sinh D – 2-2Q(cosh D – sinh D)] |D| < loge 2 cosh(Q loge 2 + D) = (2Q /2)[cosh D + sinh D + 2-2Q(cosh D – sinh D)] |D| < loge 2 tanh(Q loge 2 + D) = sinh(Q loge 2 + D) / cosh(Q loge 2 + D) |D| < loge 2 tanh-1(1 – M2-E) = tanh-1(T) + (E/2) loge 2 where T = (2 – M – M2-E) / (2 + M – M2-E) 0.17 < T < 0.75 for 0.5  M < 1, E 1 exp(Q loge 2 + D) = 2Q(cosh D + sinh D) |D| < loge 2 loge (M2E) = loge M + E loge 2 0.5  M < 1.0 sqrt(M2E) ={ 2E/2 sqrt(M) if E mod 2 = 0 } { 2(E+1)/2 sqrt (M/2) if E mod 2 = 1 } {0.5  M < 1.0 {0.25 M/2 < 0.5 (Mx2Ex)(Mz2Ez) = (MxMz)2Ex + Ez 0.5  Mz < 1.0 (My2Ey) / (Mx2Ex) = (My / 2Mx)2Ey – Ex + 1 0.25  My / 2Mx < 1.0 CORDIC – Domain Extension Page 5

  6. Sign bit Function Exponent Group Mantissa Number Number represented 0 0 0 Zero 0 255 0 +∞ Sin 000 000 1 255 0 -∞ Cos 000 001 0 or 1 255 Not 0 Not-a-number (NaN) Tan 000 010 Sinh 000 100 Cosh 000 101 Tanh 000 110 Exp 000 111 Sin-1 001 000 Cos-1 001 010 Tan-1 010 000 Tanh-1 011 000 Sqrt 100 000 Multiplication 101 000 Division 110 000 loge 111 000 Co-Processor Design Grouping of Functions Prescale000 Postscale000 CORDIC Prescale001 Postscale001 … … State machine GO Done Top-Level Diagram IEEE 754 standard compliant Page 6

  7. Generic Iterative CORDIC Module Subtracter x register  CLK ST DT M CORDIC XO Adder/subtracter YO ZO m 0 XR YR ZR C Subtracter Done y register k=32?  ST - start DT - vectoring/rotation mode M - linear/trigonometric/hyperbolic mode XR, YR, ZR – input values XO, YO, ZO – output values C – input argument Adder/subtracter Counter k 0-32 z register  Adder/subtracter Table of values for  Page 7

  8. FSM Floating-Point Addition/Subtraction SA OP Allzero SB MSB MA Shift register Add mantissa LD_A SH_A MB Shift register Shift register 0 LD_B SH_B LD_R SH_R DIR_R EA Increment/Decrement Compare GT LT LD_A EX_IA EQ EB Increment/Decrement A LD_B EX_IB EX_DB Allzero BS A 0 Allzero B Module Add_sub performing floating-point addition/subtraction of two 32-bit numbers A and B. Page 8

  9. Integration with Leon Sparc V8 Leon IP core Leon is an open-source SPARC V8 conformant soft processor core, written in VHDL, which was developed by ESA. Page 9

  10. Design Processes and Tools Software Design Hardware Design XXSV800 Page 10

  11. Command 31-30 29-25 24-19 18-14 13-5 4-0 cpop1 10 rd 110110 rs1 opc rs2 cpop2 10 rd 110111 rs1 opc rs2 Interface with the Leon IP Core Math Library Example Page 11

  12. Performance Results Page 12

  13. Conclusions • A 32-bit maths co-processor VHDL core is developed for a SoC OBC based on the Leon SPARC V8 IP core - • aimed at speeding up computationally intensive on-board applications, traditionally implemented in software, e.g ADCS. • The co-processor is fully compliant with the IEEE 754 floating-point standard and implements 17 functions: • addition, subtraction, multiplication, division, square root, sine, cosine, tangent, inverse sine, inverse cosine, inverse tan, sinh, cosh, tanh, inverse tanh, exp and ln. • The co-processor occupies half the size of a Virtex XCV800 chip. • The co-processor operates at 2.5MHz, when integrated with the Leon IP core, at 25 MHz - when standalone. • The co-processor accelerates execution of floating-point calculations on the Leon processor: • the Whetstone benchmark runs 70% faster on Leon+RTEMS+CP compared with the time it takes on Leon+RTEMS. Page 13

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