Presenter : Shoa-Chieh Hou

1. A Low-Cost SOC Debug Platform Based on On-Chip Test ArchitecturesKuen-Jong Lee, Si-Yuan Liang and Alan SuDept. EE, NCKU ; GUC Presenter : Shoa-ChiehHou SOC Conference, 2009. SOCC 2009. IEEE International 

2. Abstract While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly, today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.

3. My Related Works Tree My thesis HW side SW side GDB(SW debug) Multi-TAP controller Scan-base wrapper Trace technique Coresight…etc McMaster university DASTEP SW/HW Co-debug Platform[2012] Low-Cost SoC Test Platform[2009] ….. An Embedded Processor Based SOC Test Platform[2005]

4. Related Works This paper Infrastructures for platform Past work Run-Stop debug Platform base[9,10] Signal Trace [12] Infrastructure IPs[5] In-Circuit Emulator[3,4] Multi-Core issue NoC Debug[6] For Core[9] SoC base[10] ICE HW[3] ICE SW[4]

5. What’s the problem? • Increasing of the chip complexity • Bug also increase • Time to market • Gap between simulation and real circuits • Some problem happened in simulation, some in real IC • JTAG is widely used method • ICE • Run stop mechanism • Trace • Method for SoC full test

6. Debug Procedure • Virtual level simulation • Post-silicon debug(simulation) • Capture the simulation result as data A • On-line trace and comparison • In FPGA or real case test • Trace rough data from bus or IP I/O • Capture the result as data B • Compare data A and B, and make sure with IP had problem • HW breakpoint insertion and single stepping • Use run-stop mechanism to capture more detail data as data C • Compare data C and data A to find the error in SoC

7. Propose Platform Hardware

8. TAM Controller Calculated address and allows TAM controller to access memory Break-Point Setup Controller Send enable signal to core while TAM like a slave Generate 1149.1 control signal for scan For scan wrapper setup and output

9. Suspend & Restore Mechanism

10. Automation Tool Test Platform Integration Test Platform(HW) Test Program(SW) Debug HW Generation Debug Program(HW) Debug Library Application Program Debug SW Integration Debug Program(SW) TAMC Setup File Setup File Expected Response Extraction Debug Pattern Transformation Expected Responses Transformed patterns

11. DASTEP SW(GUI)

12. Experimental Results

13. Conclusion • The paper propose • Full system for SoC test and debug • Automation tool for environment build • Allow multi-core trace and run-stop debug • Low cost in total SoC area

14. My Comment • Platform is like our debug environment • JTAG base • Multi JTAG port • TAM controller architecture can be use in our environment • Modify for simple • Buffer, B.P., shift mechanism design can be reference

15. TMS TCK_1 …... TCK TCK_N TRST_1 …... TRST TRST_N buffer TDI_1 …... TDI(with ID) TDI(without ID) TDI_N ID Decoder ID TDO_1 Encoder …...... …...... TDO(with ID) TDO TDO_N

16. TAP controller Core TAP #1 TCK_1 TRST_1 TCK TMS TDI_1 TDO_1 TRST …………………………. TMS Core TAP #N TCK_N TDI(with ID) TRST_N TMS TDI_N TDO(with ID) TDO_N