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Test and Evaluation of HAL25 The ALICE SSD Front-End Chip

Test and Evaluation of HAL25 The ALICE SSD Front-End Chip. C. Hu-Guo , D. Bonnet, J.P. Coffin, G. Deptuch, C. Gojak, J.R. Lutz, I. Valin IReS (IN2P3-ULP), Strasbourg, France J.D. Berst, G. Claus, C. Colledani LEPSI (IN2P3-ULP), Strasbourg, France. HAL25 History.

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Test and Evaluation of HAL25 The ALICE SSD Front-End Chip

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  1. Test and Evaluation of HAL25 The ALICE SSD Front-End Chip C. Hu-Guo, D. Bonnet, J.P. Coffin, G. Deptuch, C. Gojak, J.R. Lutz, I. Valin IReS (IN2P3-ULP), Strasbourg, France J.D. Berst, G. Claus, C. Colledani LEPSI (IN2P3-ULP), Strasbourg, France Christine HU-GUO

  2. HAL25 History • 1st generation chip: ALICE128C (1997) • Designed on a CMOS 1.2 mm process • Good performance up to 50 Krad of the ionising dose • Used for the SSD front-end of the STAR tracker • HAL25 • Designed on a deep submicron 0.25 mm process • For safety margins in radiation environment • Version 1 (MPW4-March-2001) • Version 2 (MPW6-November-2001) Christine HU-GUO

  3. 127 127 127 127 P TEMPO AIN<127> <1:0> U A | P L N | + U P R A S A N L O E | _ S W A ANALOGUE CHANNELS E OUTBUF E E D O M R O U | R O U T G U - | E N T E X G | OUTBUF N AIN<0> 0 CTRL<1:0> 0 0 0 BIAS GENERATORS BIAS PULSE PULSE BIAS DAC<71:0> DAC<7:0> BYPASS<0> BSR<5:0> ID<7:0> STATUS<7:0> POWER_ENA<0> TOKEN_ENA<0> JTAG CONTROLER Analogue Sig. TDI LVDS Sig. TCK TDO TMS RCLK HOLD TK_IN PULSE TRSTB FSTRB ID<3:0> TK_OUT GNDREF PWRSTB CMOS Sig. HAL25 Block Diagram • - 128 Analogue Channels: • Preamplifier • Shaper • Storage capacitor • - Analogue Multiplexer • Differential Current Output • 128 Test Pulse Generators JTAG remote control • Set Bias Generator • Set Transparent Mode • Set Test Pulse Generator • Perform Boundary Scan Christine HU-GUO

  4. Design Features in HAL25 • Single power supply 0-2.5 V •  14 MIP dynamic range front-end amplifier • Differential current output • Registers with majority vote logic • Prevent Single Event Upset (SEU) • Adjustable internal current source (15%) • Compensate process variation Christine HU-GUO

  5. V dc Vdc N VPRE Cf1 Cf2 Hold Cc OUT IN Cload Vdc P Front-end Amplifier • Shaper feedback resistor  source degenerated differential pair • No “switch+inverter” circuitry • Vout = Vdc (DC level) • Maximum dynamic range ( 14 MIP ) for GV = 50 mV/MIP • Linearity < 4% • Tuneable transconductance • Tuneable peaking time 1.4ms < t < 2.2 ms Christine HU-GUO

  6. HAL25 Layout • Chip dimension: 3.65 x 11.90 mm2 • TAB compatibleI/O pads • Size & pitche • ESD protected I/O Pads • CMOS for slow control • LVDS for readout Christine HU-GUO

  7. Output diff (mA) 250 -250 Pedestal Distribution • For 1 chip (128 channels ) • I  34 mA • 1 MIP signal • After pedestal subtraction Christine HU-GUO

  8. Gain & linearity Current! • Agree with simulation • Measured pulse fit ideal CRRC curve • GI= 200-250 A / MIP (22000 e-) • Dynamic range ± 14 MIP • Linearity < 2.5% ( ± 10 MIP) & Linearity < 4% ( ± 14 MIP) Christine HU-GUO

  9. Analogue channel + test pulse generator Output Pulse Uniformity (MPW6 run) • With the internal test pulse generator  8 MIP signal • 62 chips x 128 ch (on 2 wafers) • Average output pulse amplitude  1875 mA •   63 mA Good uniformity Christine HU-GUO

  10. Bonded channel (1.5 pF) Noise • Noise distribution (128 ch) • ENC @ 0pF = 215 e- • s = 5 e- • ENC = 215 + 25 e-/pF • For peaking time 1.4 ms Christine HU-GUO

  11. FRd = 1 MHz Input = 10 MIP FRd = 10 MHz Input = 10 MIP Ch. 10 Ch. 11 Ch.12 Ch. 10 Ch. 11 Ch.12 FRd = 20 MHz Input = 10 MIP FRd = 30 MHz Input = 10 MIP Ch. 10 Ch. 11 Ch.12 Ch. 10 Ch. 11 Ch.12 Maximum readout frequency • Nominal readout frequency: 10 MHz • Readout up to 20 MHz with degradation of • Linearity & Gain Christine HU-GUO

  12. VPRE New Request for High Input Rate • Pile-up depends on • Input signal time intervals • Input signal amplitudes • Decay times • Preamplifier decay time • Nominal: a few ms ( hundreds Hz) • Can be decreased by changing VPRE  Rf = f(VPRE) • Noise increased • Gain reduced • Shaper decay time •  8*peaking time ( few tens KHz) Ref. “Pile-up phenomena in HAL25” ftp://lepsi.in2p3.fr/pub/HAL25/Pile_up.pdf Christine HU-GUO

  13. Yield • 340 circuits tested from 2 MPW •  50% OK • Problem seems to be related to • 128 channels architecture for deep sub-micron process • Long lines for common biases and slow signals • No errors detected by Design Rule Checkers • 0.25mm community investigates the problem • New version of HAL25 • intended to understand yield issue Christine HU-GUO

  14. Conclusion • HAL25 meets specifications • Irradiation test with X-ray up to 500 Krad • No performance degradation • Version 3 (MPW8 – September 2002) • Focused on yield improvement • ESD I/O Pads • Low power LVDS Pads • Fuse programmable chip serial number (24 bit) • Future work • Test  HAL25 + Detector Christine HU-GUO

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