1 / 63

CPE 528: Session #8

CPE 528: Session #8. Department of Electrical and Computer Engineering University of Alabama in Huntsville. Outline. Files Notes on VHDL Synthesis. Files. File input/output in VHDL Used in test benches Source of test data Storage for test results VHDL provides a standard TEXTIO package

franklinrobert
Download Presentation

CPE 528: Session #8

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CPE 528: Session #8 Department of Electrical and Computer Engineering University of Alabama in Huntsville

  2. Outline • Files • Notes on VHDL Synthesis UAH-CPE528

  3. Files • File input/output in VHDL • Used in test benches • Source of test data • Storage for test results • VHDL provides a standard TEXTIO package • read/write lines of text UAH-CPE528

  4. Files (cont’d) • VHDL defines a file object, associated types, and certain limited file operations • File declarations • VHDL87 • VHDL93 TYPE file_type IS FILE OF type_mark; PROCEDURE READ(FILE identifier : file_type; value : OUT type_mark); PROCEDURE WRITE(FILE identifier : file_type; value : IN type_mark); FUNCTION ENDFILE(FILE identifier : file_type) RETURN BOOLEAN; FILE identifier : file_type IS [mode] “file_name”; FILE identifier : file_type [[OPEN mode] IS “file_name”]; UAH-CPE528

  5. Files (Cont’d) • VHDL 87 - files are opened and closed when the associated file object comes into and goes out of scope • VHDL 93 -- opens a file for reading FILE in_file:bit_file IS “my_file.dat” -- opens a file for writing FILE out_file:bit_file IS OUT “my_other_file.dat”; -- opens a file for reading FILE in_file:bit_file OPEN READ_MODE IS “my_file.dat”; -- Or simply declared (and named and opened later): FILE out_file:bit_file; UAH-CPE528

  6. File Opening and Closing • In VHDL93, files can be opened in the declaration or predefined procedures can be used: • The values for FILE_OPEN_KIND are:READ_MODE, WRITE_MODE, and APPEND_MODE • The values for FILE_OPEN_STATUS are: OPEN_OK, STATUS_ERROR, NAME_ERROR, and MODE_ERROR PROCEDURE FILE_OPEN(FILE identifier:file_type; file_name: IN STRING; open_kind: FILE_OPEN_KIND := READ_MODE); PROCEDURE FILE_OPEN(status: OUT FILE_OPEN_STATUS; FILE identifier: file_type; file_name: IN STRING; open_kind: FILE_OPEN_KIND := READ_MODE); PROCEDURE FILE_CLOSE(FILE identifier: file_type); UAH-CPE528

  7. Text Input and Output • Basic file operations in VHDL are limited to unformatted input/output • VHDL includes the TEXTIO package for input and output of ASCII text • TEXTIO is located in the STD library • The following data types are supported by the TEXTIO routines: • Bit, Bit_vector • Boolean • Character, String • Integer, Real • Time USE STD.TEXTIO.ALL; UAH-CPE528

  8. TEXTIO Procedures • TEXTIO defines a LINE data type • All read and write operations use the LINE type • TEXTIO also defines a FILE type of TEXT for use with ASCII text • Procedures defined by TEXTIO are: • READLINE(f,k) • reads a line of file f and places it in buffer k • READ(k,v,...) • reads a value of v of its type from k • WRITE(k,v,...) • writes value v to LINE k • WRITELINE(f,k) • writes k to file f • ENDFILE(f) returns TRUE at the end of FILE UAH-CPE528

  9. Using TEXTIO • Reading from a file • READLINE reads a line from the file into a LINE buffer • READ gets data from the buffer • Writing to a file • WRITE puts data into a LINE buffer • WRITELINE writes the data in the LINE buffer to file • READ and WRITE have several formatting parameters • Right or left justification • Field width • Unit displayed (for time) UAH-CPE528

  10. TEXTIO: Example 1 • This procedure displays the current state of a FSM USE STD.TEXTIO.ALL; --TEXTIO package is available TYPE state IS (reset, good); - new type state is declared PROCEDURE display_state (current_state : IN state) IS VARIABLE k : LINE; -- buffer k of type LINE -- file flush is of type TEXT and will output to console FILE flush : TEXT IS OUT "/dev/tty"; VARIABLE state_string : STRING(1 to 7); -- text value BEGIN CASE current_state IS WHEN reset => state_string := "reset "; WHEN good => state_string := "good "; END CASE; WRITE (k, state_string, LEFT, 7); --left justified, 7s WRITELINE (flush, k); -- send buffer to file flush END display_state; If we call this procedure again ... UAH-CPE528

  11. TextIO: Read_v1d procedure read_v1d (variable f :in text ; v : out std_logic_vector ) is variable buf : line; variable c : character ; begin -- do not forget appropriate library declarations readline (f , buf ); --read a line from the file. for i in v ’range loop read( buf , c ) ; --read a character from the line. case c is when ‘ X ’ => v (i) := ‘ X ’ ; when ‘ U ’ => v (i) := ‘ U ’ ; when ‘ Z ’ => v (i) := ‘ Z ’ ; when ‘ 0 ’ => v (i) := ‘ 0 ’ ; when ‘ 1 ’ => v (i) := ‘ 1 ’ ; when ‘ -’ => v (i):= ‘ -’ ; when ‘ W ’ => v (i) := ‘ W ’ ; when ‘ L ’ => v (i) := ‘ L ’ ; when ‘ H ’ => v (i) := ‘ H ’ ; when others => v (i) := ‘ 0 ’; end case; end loop; end; UAH-CPE528

  12. Longer TextIO example -- square the value int_val := int_val **2; -- write the squared value to the line WRITE( out_line, int_val); -- write the line to the output file WRITELINE( outfile, out_line); END LOOP; END PROCESS; END simple; LIBRARY IEEE; USE STD.TEXTIO.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE IEEE.STD_LOGIC_1164.ALL; ENTITY square IS PORT( go : IN std_logic); END square; ARCHITECTURE simple OF square IS BEGIN PROCESS(go) FILE infile : TEXT IS IN "/pp/test/example1"; FILE outfile : TEXT IS OUT "/pp/test/outfile1"; VARIABLE out_line, my_line : LINE; VARIABLE int_val : INTEGER; BEGIN WHILE NOT( ENDFILE(infile)) LOOP -- read a line from the input file READLINE( infile, my_line); -- read a value from the line READ( my_line, int_val); UAH-CPE528

  13. An Example • Procedure to read data from a file and store the data in a memory array • Format of the data in the file • address N commentsbyte1 byte2 ... byteN comments • address – 4 hex digits • N – indicates the number of bytes of code • bytei - 2 hex digits • each byte is separated by one space • the last byte must be followed by a space • anything following the last state will not be read and will be treated as a comment UAH-CPE528

  14. An Example (cont’d) • Code sequence: an example • 12AC 7 (7 hex bytes follow)AE 03 B6 91 C7 00 0C (LDX imm, LDA dir, STA ext)005B 2 (2 bytes follow)01 FC_ • TEXTIO does not include read procedure for hex numbers • we will read each hex value as a string of charactersand then convert the string to an integer • How to implement conversion? • table lookup – constant named lookup is an array of integers indexed by characters in the range ‘0’ to ‘F’ • this range includes the 23 ASCII characters:‘0’, ‘1’, ... ‘9’, ‘:’, ‘;’, ‘<‘, ‘=‘, ‘>’, ‘?’, ‘@’, ‘A’, ... ‘F’ • corresponding values:0, 1, ... 9, -1, -1, -1, -1, -1, -1, -1, 10, 11, 12, 13, 14, 15 UAH-CPE528

  15. VHDL Code to Fill Memory Array UAH-CPE528

  16. VHDL Code to Fill Memory Array (cont’d) UAH-CPE528

  17. Notes on VHDL Synthesis Department of Electrical and Computer Engineering University of Alabama in Huntsville

  18. Outline • VHDL Packages for Synthesis • VHDL for Combinational Logic Synthesis • VHDL for Sequential Logic Synthesis • VHDL for RTL Level Synthesis • Structural VHDL • Implementation Technology Considerations • Summary

  19. VHDL Packages for SynthesisBase Types • Standard bit types may be used • Typically IEEE 1164 Std. types are used • std_ulogic type • Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for synthesis USE IEEE.std_logic_1164.ALL; TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); • std_logic type - resolved std_ulogic type

  20. VHDL Packages for SynthesisBase Types (cont.) • The std_logic_1164 package also contains: • Vectors of std_ulogic and std_logic • Subtypes of std_logic - X01, X01Z, UX01, UX10Z • Logic functions with various arguments - std_ulogic, std_logic, std_logic_vector FUNCTION “and” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nand” (l,r : std_ulogic;) RETURN UX01; FUNCTION “or” (l,r : std_ulogic;) RETURN UX01; FUNCTION “nor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xor” (l,r : std_ulogic;) RETURN UX01; FUNCTION “xnor” (l,r : std_ulogic;) return ux01; FUNCTION "not" (l,r : std_ulogic) RETURN UX01; • Conversion functions FUNCTION To_bit(s:std_ulogic) RETURN bit; FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector; FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;

  21. VHDL Packages for SynthesisBase Types (cont.) • Unknown functions • Clock edge functions FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean; FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean; FUNCTION Is_X (s:std_logic_vector) RETURN boolean; FUNCTION Is_X (s:std_ulogic) RETURN boolean;

  22. VHDL Packages for SynthesisArithmetic Packages • All synthesis tools support some type of arithmetic packages • Synopsis developed packages based on std_logic_1164 package - supported by many other synthesis tools • std_logic_arith • std_logic_signed • std_logic_unsigned • Actel synthesis tools support their own package • asyl.arith • IEEE has developed standard packages for synthesis IEEE Std. 1076.3 • Numeric_Bit • Numeric_Std UAH-CPE528

  23. IEEE Std 1076.3 PackagesNumeric_Bit • Type declarations for signed and unsigned numbers USE IEEE.numeric_bit.ALL; TYPE unsigned IS ARRAY (natural RANGE <> ) OF bit; TYPE signed IS ARRAY (natural RANGE <> ) OF bit; • Arithmetic operators - various combinations of signed and unsigned arguments FUNCTION “abs” (arg:unsigned) RETURN unsigned; FUNCTION “-” (arg:unsigned) RETURN unsigned; FUNCTION “+” (l,r:unsigned) RETURN unsigned; FUNCTION “-” (l,r:unsigned) RETURN unsigned; FUNCTION “*” (l,r:unsigned) RETURN unsigned; FUNCTION “/” (l,r:unsigned) RETURN unsigned; FUNCTION “rem” (l,r:unsigned) RETURN unsigned; FUNCTION “mod” (l,r:unsigned) RETURN unsigned; UAH-CPE528

  24. IEEE Std 1076.3 PackagesNumeric_Bit • Comparison operators - various combinations of signed and unsigned arguments FUNCTION “>” (l,r:unsigned) RETURN boolean; FUNCTION “<” (l,r:unsigned) RETURN boolean; FUNCTION “<=” (l,r:unsigned) RETURN boolean; FUNCTION “>=” (l,r:unsigned) RETURN boolean; FUNCTION “=” (l,r:unsigned) RETURN boolean; FUNCTION “/=” (l,r:unsigned) RETURN boolean; • Shift and rotate functions FUNCTION shift_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION shift_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_left (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rotate_right (arg:unsigned; count:natural) RETURN unsigned; FUNCTION sll (arg:unsigned; count:natural) RETURN unsigned; FUNCTION slr (arg:unsigned; count:natural) RETURN unsigned; FUNCTION rol (arg:unsigned; count:natural) RETURN unsigned; FUNCTION ror (arg:unsigned; count:natural) RETURN unsigned; UAH-CPE528

  25. IEEE Std 1076.3 PackagesNumeric_Bit • Resize functions FUNCTION resize (arg:unsigned;new_size:natural) RETURN unsigned; FUNCTION resize (arg:signed;new_size:natural) RETURN signed; • Conversion functions FUNCTION to_integer (arg:unsigned) RETURN natural; FUNCTION to_unsigned (arg,size:natural) RETURN unsigned; • Logical operators FUNCTION “not” (l:unsigned) RETURN unsigned; FUNCTION “and” (l,r:unsigned) RETURN unsigned; FUNCTION “or” (l,r:unsigned) RETURN unsigned; FUNCTION “nand” (l,r:unsigned) RETURN unsigned; FUNCTION “nor” (l,r:unsigned) RETURN unsigned; FUNCTION “xnor” (l,r:unsigned) RETURN unsigned; • Edge detection functions FUNCTION rising_edge(SIGNAL s:bit) RETURN boolean; FUNCTION falling_edge(SIGNAL s:bit) RETURN boolean; UAH-CPE528

  26. IEEE Std 1076.3 PackagesNumeric_Std • Similar to Numeric_Bit package using std_logic_1164 types • Signed and unsigned type declarations • Aritmetic operators • Comparison operators • Shift and rotate functions • Resize functions • Conversion functions • Logical operators • Match functions USE IEEE.numeric_std.ALL; FUNCTION std_match (l,r:std_ulogic) RETURN boolean; FUNCTION std_match (l,r:unsigned) RETURN boolean; • Translation functions FUNCTION to_01 (s:unsigned; xmap:std_logic := ‘0’) RETURN unsigned; UAH-CPE528

  27. Outline • VHDL Packages for Synthesis • VHDL for Combinational Logic Synthesis • Types • Attributes • Concurrent signal assignment statements • Operators • Processes • If statements • Case statements • Loops • Procedures and functions • Tri state logic • Use of don’t cares • After clauses • Inferring latches • Problems to avoid • VHDL for Sequential Logic Synthesis • VHDL for RTL Level Synthesis

  28. Types • Scalar types • Enumeration types are supported • Bit, Boolean, and Std_Ulogic map to single bits • Mapping of other types will be made by the tool unless the ENUM_ENCODING attribute is used • Character type is suppored • Severity_level type is ignored • Integer type, Natural, and Positive are supported • A subtype with a descrete range should be used or the default 32 bit length will be synthesized • Physical types (e.g., time) are ignored • Floating point type is ignored - references to floating point objects can occur only within ignored constructs, e.g., After clauses, etc. UAH-CPE528

  29. Types (cont.) • Array types are supported • Bounds must be specified directly or indirectly as static values of an integer type • Element subtype must denote a scalar type or a one dimensional vector of an enumerated type that denotes single bits TYPE integer_array IS ARRAY(natural RANGE 7 DOWNTO 0) OF integer; TYPE boolean_array IS ARRAY(integer RANGE <>) OF boolean; ... SIGNAL bool_sig : boolean_array(-1 to 1); • Record types are supported • Access types are ignored • File types are ignored • File objects and file operations are not supported UAH-CPE528

  30. Attributes • The following predefined attributes for types are supported: • t’BASE • t’LEFT • t’RIGHT • t’HIGH • t’LOW • The following predefined attributes for array objects are supported: • a’LEFT • a’RIGHT • a’HIGH • a’LOW • a’RANGE • a’REVERSE_RANGE • a’LENGTH • The following predefined attributes for signals are supported • s’STABLE • s’EVENT • User defined attributes other than ENUM_ENCODING are NOT supported UAH-CPE528

  31. Concurrent Signal Assignment Statements • Simple concurrent signal assignment statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_csa is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_csa; ARCHITECTURE behavior OF aoi_csa IS SIGNAL sig1,sig2 : std_logic; BEGIN sig1 <= a AND b; sig2 <= c OR sig1; y <= NOT sig2; END behavior; library IEEE; use IEEE.std_logic_1164.all; ENTITY csa is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END csa; ARCHITECTURE behavior OF csa IS BEGIN y <= a NOR b; END behavior; UAH-CPE528

  32. Conditional Signal Assignment Statements • Concurrent conditional signal assignment statements are supported - must end inelseclause library IEEE; use IEEE.std_logic_1164.all; ENTITY mux2 is PORT(a : IN std_logic; b : IN std_logic; sel : IN std_logic; y : OUT std_logic); END mux2; ARCHITECTURE behavior OF mux2 IS BEGIN y <= a WHEN (sel = '0') ELSE b WHEN (sel = '1') ELSE 'X'; END behavior; UAH-CPE528

  33. Selected Signal Assignment Statements • Concurrent selected signal assignment statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4 is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4; ARCHITECTURE behavior OF mux4 IS BEGIN WITH sel SELECT y <= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN "11", 'X' WHEN OTHERS; END behavior; UAH-CPE528

  34. Operators • Generally, if the numeric_bit and numeric_std packages are supported, the operators within them are supported • Arithmetic operators - “abs”, “+”, “-”, “*”, “/”, “rem”, “mod” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY divider is PORT(divisor : IN unsigned(1 DOWNTO 0); dividend : IN unsigned(1 DOWNTO 0); quotient : OUT unsigned(1 DOWNTO 0)); END divider; ARCHITECTURE behavior OF divider IS BEGIN quotient <= dividend / divisor; END behavior; UAH-CPE528

  35. Operators (cont.) • Comparison operators - “>”, “<“, “<=“, “>=“, “=“, “/=“ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY compare is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(3 DOWNTO 0); aleb : OUT boolean); END compare; ARCHITECTURE behavior OF compare IS BEGIN aleb <= (a <= b); END behavior; UAH-CPE528

  36. Operators (cont.) • Shift and conversion operators - “shift_left”, “shift_right”, “rotate_left”, “rotate_right”, “resize”, “to_integer”, “to_unsigned” library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY shift_4 is PORT(a : IN unsigned(3 DOWNTO 0); b : IN unsigned(1 DOWNTO 0); y : OUT unsigned(3 DOWNTO 0)); END shift_4; ARCHITECTURE behavior OF shift_4 IS BEGIN y <= shift_left(a,to_integer(b)); END behavior; UAH-CPE528

  37. Process Statements • Process statements are supported • Postponed processes (or postponed concurrent signal assignment statements) are NOT supported • Process statement can have either a sensitivity list or a WAIT statement • Sensitivity list is ignored for synthesis (by most tools) - thus, to avoid simulation mismatches, all signals which appear on the RHS should be in the sensitivity list • Only one WAIT statement per process is allowed and it must be the first statement in the process after BEGIN • Only the WAIT UNTIL syntax of the WAIT statement is supported WAIT UNTIL input1 = ‘1’; WAIT UNTIL clock’EVENT and clock = ‘1’; UAH-CPE528

  38. Process StatementsExample library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c,sig1) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; UAH-CPE528

  39. a b 0 c sig1 U y 0 5 10 15 20 Process StatementsIncomplete Sensitivity List library IEEE; use IEEE.std_logic_1164.all; ENTITY aoi_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END aoi_process; ARCHITECTURE behavior OF aoi_process IS SIGNAL sig1 : std_logic; BEGIN comb : PROCESS(a,b,c) BEGIN sig1 <= a AND b; y <= not(sig1 or c); END PROCESS comb; END behavior; UAH-CPE528

  40. Sequential Signal Assignment Statements • Various types of signal assignment statements inside a process statement (sequential signal assignment statements) are supported • IF statements • Case statements • Loop statement • Only For loops supported • Bounds must be specified as static values of an integer type • Exit and Next statements supported (without lables) UAH-CPE528

  41. Sequential IF Statements • IF statements are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY xor_process is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END xor_process; ARCHITECTURE behavior OF xor_process IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= '0'; END IF; END PROCESS comb; END behavior; UAH-CPE528

  42. Sequential Case Statements library IEEE; use IEEE.std_logic_1164.all; ENTITY mux4_process is PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; d : IN std_logic; sel : IN std_logic_vector(1 DOWNTO 0); y : OUT std_logic); END mux4_process; ARCHITECTURE behavior OF mux4_process IS BEGIN comb : PROCESS(a,b,c,d,sel) BEGIN CASE sel IS WHEN "00" => y <= a; WHEN "01" => y <= b; WHEN "10" => y <= c; WHEN "11" => y <= d; WHEN OTHERS => y <= 'X'; END CASE; END PROCESS comb; END behavior; • Case statements are supported • Choices which include metalogical values are never taken UAH-CPE528

  43. Sequential Loop Statements • Only For loops with integer range are supported library IEEE; use IEEE.std_logic_1164.all; ENTITY shift4 is PORT(mode : IN std_logic; shift_in : IN std_logic; a : IN std_logic_vector(4 DOWNTO 1); y : OUT std_logic_vector(4 DOWNTO 1); shift_out : OUT std_logic); END shift4; ARCHITECTURE behavior OF shift4 IS SIGNAL in_temp : std_logic_vector(5 DOWNTO 0); SIGNAL out_temp : std_logic_vector(5 DOWNTO 1); BEGIN in_temp(0) <= shift_in; in_temp(4 DOWNTO 1) <= a; in_temp(5) <= '0'; comb : PROCESS(mode,in_temp,a) BEGIN FOR i IN 1 TO 5 LOOP IF(mode = '0') THEN out_temp(i) <= in_temp(i-1); ELSE out_temp(i) <= in_temp(i); END IF; END LOOP; END PROCESS comb; y <= out_temp(4 DOWNTO 1); shift_out <= out_temp(5); END behavior; UAH-CPE528

  44. Procedures and Functions • Procedures and Functions are supported - with limitations to allowed statement types • Procedures and functions may be in a package or in the declarative part of the architecture LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; PACKAGE logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic; PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)); END logic_package; UAH-CPE528

  45. Procedures and Functions (cont.) PACKAGE BODY logic_package IS FUNCTION majority(in1, in2, in3 : std_logic) RETURN std_logic IS VARIABLE result : std_logic; BEGIN IF((in1 = '1' and in2 = '1') or (in2 = '1' and in3 = '1') or (in1 = '1' and in3 = '1')) THEN result := '1'; ELSIF((in1 = '0' and in2 = '0') or (in2 = '0' and in3 = '0') or (in1 = '0' and in3 = '0')) THEN result := '0'; ELSE result := 'X'; END IF; RETURN result; END majority; UAH-CPE528

  46. Procedures and Functions (cont.) PROCEDURE decode(SIGNAL input : IN std_logic_vector(1 DOWNTO 0); SIGNAL output : OUT std_logic_vector(3 DOWNTO 0)) IS BEGIN CASE input IS WHEN "00" => output <= "0001"; WHEN "01" => output <= "0010"; WHEN "10" => output <= "0100"; WHEN "11" => output <= "1000"; WHEN OTHERS => output <= "XXXX"; END CASE; END decode; END logic_package; UAH-CPE528

  47. Using Procedures and Functions LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY voter IS PORT(a : IN std_logic; b : IN std_logic; c : IN std_logic; y : OUT std_logic); END voter; ARCHITECTURE maj OF voter IS BEGIN y <= majority(a,b,c); END maj; UAH-CPE528

  48. Using Procedures and Functions (cont.) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; USE work.logic_package.all; ENTITY decoder IS PORT(y : IN std_logic_vector(1 DOWNTO 0); g : OUT std_logic_vector(3 DOWNTO 0)); END decoder; ARCHITECTURE dec OF decoder IS BEGIN comb : PROCESS(y) BEGIN decode(y,g); END PROCESS comb; END dec; UAH-CPE528

  49. Tri-State Logic • Tri-state logic is infered when an object is assigned an IEEE Std. 1164 value ‘Z’ library IEEE; use IEEE.std_logic_1164.all; ENTITY tri_state4 is PORT(enable : IN std_logic; a : IN std_logic_vector(3 DOWNTO 0); y : OUT std_logic_vector(3 DOWNTO 0)); END tri_state4; ARCHITECTURE behavior OF tri_state4 IS BEGIN y <= a WHEN (enable = '1') ELSE "ZZZZ"; END behavior; UAH-CPE528

  50. Use of Don’t Cares (‘X’s) • IEEE Std. 1164 values of ‘X’ or ‘-’ can be used to specify “don’t care” conditions library IEEE; use IEEE.std_logic_1164.all; ENTITY not_xor is PORT(a : IN std_logic; b : IN std_logic; y : OUT std_logic); END not_xor; ARCHITECTURE behavior OF not_xor IS BEGIN comb : PROCESS(a,b) BEGIN IF((a = '1' and b = '0') OR (a = '0' and b = '1')) THEN y <= '1'; ELSE y <= 'X'; -- could also be ‘-’ END IF; END PROCESS comb; END behavior; UAH-CPE528

More Related