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S caleable A rchitecture for R eal-Time A pplications, SARA

S caleable A rchitecture for R eal-Time A pplications, SARA. Lennart Lindh, Tommy Klevin and Johan Furunäs, Department of Computer Engineering (IDT), Mälardalens Real-Time Center (MRTC) Mälardalens University, Sweden (http://www.mrtc.mdh.se/cal/). Application Control System.

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S caleable A rchitecture for R eal-Time A pplications, SARA

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  1. Scaleable Architecture for Real-Time Applications, SARA Lennart Lindh, Tommy Klevin and Johan Furunäs, Department of Computer Engineering (IDT), Mälardalens Real-Time Center (MRTC) Mälardalens University, Sweden (http://www.mrtc.mdh.se/cal/)

  2. ApplicationControl System

  3. “Robot” Problems Today • Performance (>3 Processors today) • Functionality in the base system (RTOS) • Communication protocol • Static coupled multi-processor system • We have added: • Predictability (robotics have some hard deadlines) • Observability and controllability • Small Overhead (simplification) • Fault Tolerance • Component oriented design

  4. Mixed HW/SW implementation Hardware Hardware Hardware Software Hardware Software Software The research question is: will it be possible to meet the SARA’s objectives if software functions and functions implements in hardware?

  5. Yesterday, Today and Tomorrow

  6. Presentation of SARA,Scaleable Architecture for Real-Time Applications • The SARA Approach • Logical and physical architecture • Hardware and Software • Some benchmark results • Conclusions

  7. SARA Approach (main objectives) • Performance • Scalability • Predictability (HW/SW) • Simple • Observability and controllability • Component oriented design • “adapter” for different standards • Fault Tolerance

  8. Logical architecture

  9. Priority inheritanceof the mail priorities  IPC-SEND // For asynchrony messages IPC-SENDWAIT// For synchrony messages IPC-BROADCAST// For broadcast messages  IPC-DISTRIBUTE//For multicast messages Event A, Low priority Event B, High priority Tasks (Servers)

  10. Hard tasks (Servers) • Hardware design • Formal methods Deadline controls8-16 bits applications Hardware Task Software part for the IPC bus IPC Bus Hardware part for the IPC bus

  11. Use of old software Old Application Old RTOS Software part for the IPC bus IPC Bus Hardware part for the IPC bus

  12. Physical architecture System on a Chip Standard systems Write/Read PPC750, L1,L2

  13. Hardware and Software

  14. CPU RTU-gränssnitt Avbrottsrutin för taskswitch Communication between RTU and CPU RTU HW-Interrupt CPU IRQ Handler RTU-I/O RT-clock Semaphore Scheduler Task switch handler

  15. mult_resp2 (utan Cach) task1 470.7 s task2 634.4 s mult_resp2 (with Cach) task1 452.9 s task2 602.9 s mult_resp2 task1 156,2 s task2 326,5 s IRQ-HandlerHardware and Software

  16. Kernel Overhead in Hardware

  17. Conclusion • The IPC is easy to use • When a software function implements in hardware the response time and time gap between best and worst case execution time decrease, ex in RTU clock tick is 1us, in a software system 1ms. (RTU need 5 MHz) • Demonstration of the SARA on SNART. • Are you interesting in corporation?

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