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J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL

Design for Test Seminar. Overview of the IEEE 1149.x test standards. J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL Tel. 351 225 081 889 / Fax: 351 225 081 443 (jmf@fe.up.pt / http://www.fe.up.pt/~jmf).

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J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL

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  1. Design for Test Seminar Overview of the IEEE 1149.x test standards J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL Tel. 351 225 081 889 / Fax: 351 225 081 443 (jmf@fe.up.pt / http://www.fe.up.pt/~jmf)

  2. Boundary-scan (1149.1)Mixed-signal (1149.4)AC testing (1149.6) • Why and where to use? • The BS test principle • Test access port and BS architecture • BS instructions

  3. Why Boundary Scan Test? • The two main reasons that led in the mid-80s to the development of BST were: • The complexity of ICs made it exceedingly difficult to develop test programs for the functional test of complex PCBs • Small outline surface mount devices and advanced mounting technologies almost disabled physical access to internal PCB nodes and made in-circuit test exceedingly difficult

  4. The application domain of BST • BST addresses the structural test of digital printed circuit boards • Keywords: structural, digital, PCBs • This embedded test infrastructure is now used for other purposes as well (e.g. in-system programming)

  5. The BS test principle • BS uses a Test Access Port (TAP) to decouple the internal IC logic from the pins and allows “direct” access to any PCB node without backdriving effects

  6. The BS architecture • Main blocks: • BST register • BP register • Instruction register • TAP controller • Other registers

  7. The basic BS cell • Three modes of operation: • Transparency • Controllability • Observability

  8. TAP controller state transition diagram

  9. BST instructions • Mandatory: • EXTEST • SAMPLE / PRELOAD • BYPASS • Optional: • INTEST, RUNBIST, CLAMP, IDCODE,USERCODE, HIGHZ

  10. Boundary-scan (1149.1)Mixed-signal (1149.4)AC testing (1149.6) • 1149.4: an extension of 1149.1 • TBIC and ABMs (internal test circuitry) • The PROBE instruction • Parametric testing

  11. The IEEE 1149.4 standard for mixed signal test • The 1149.4 std defines an extension to 1149.1, to which it adds: • An analog test port (ATAP)with two pins (AT1, AT2) • An internal analog test bus(AB1, AB2) • A test bus interface circuit (TBIC) • The analog boundary modules (ABM)

  12. The test bus interface circuit (TBIC) • The TBIC defines the interconnections between the ATAP (AT1 and AT2) and the internal analog test bus (at least two lines, AB1 and AB2) • The TBIC comprises a switching structure and a control structure

  13. TBIC: The switching structure

  14. TBIC: Control structure

  15. The analog boundary modules (ABM) • The ABMs in the analog pins extend the test functions made available by the DBMs • All test operations combine digital (via TAP) and analog test “vectors” (via ATAP) • Each ABM comprises a switching structure and a control structure

  16. ABMs: Switching structure

  17. ABMs: Control structure

  18. The 1149.4 register structure • The 1149.4 register structure is entirelydigital and identicalto the corresponding1149.1 structure

  19. The PROBE instruction • The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE: • The selected data register is the BS register • One or both of the ATAP pins connect to the corresponding AB1/AB2 internal test bus lines • Analog pins connect to the core and to AB1/AB2 as defined by the ABM 4-bit control word • Each DBM operates in transparent mode

  20. ZD = VT / ITif: • ZV >> ZS6 + ZSB2 • ZV + ZS6 + ZSB2 >> ZD IT ZD V VT Impedance measurement between pin and ground

  21. Boundary-scan (1149.1)Mixed-signal (1149.4)AC testing (1149.6) • Scope and objectives • Test of AC-coupled differential networks • 1149.6 test cells and instructions

  22. Scope and objectives • Scope of 1149.6: Structural test of high-speed digital networks • Objectives • Cope with differential and/or AC-coupled interconnections, enabling high fault coverage with minimum impact on mission logic • Reuse as much as possible IEEE 1149.1 tools (ensure compatibility with 1149.1 / 4)

  23. AC-coupling, differential signalling • Single-ended signalling with AC-coupling • Differential signalling with AC-coupling and bias provision TX: RX:

  24. Testing AC-coupled / differential networks • BS cell placement has an impact on circuit performance and defect coverage • Modified BS cells must ensure: • Signal transmission over AC-coupled nets • Logic level detection from AC test signals

  25. 1149.6 test cells • An AC testing instruction selects the AC Mode, and a test signal suited for AC-coupled networks is applied to the pin • A test receiver at the input cell derives logic level information from the incoming AC / DC test signal(valid transitions)

  26. 1149.6 instructions • EXTEST_PULSE generates a transition even when the new test value at the driver pin retains its previous value • EXTEST_TRAIN provides multiple additional transitions (to cope with transient conditions, when necessary) • Both cause the driver pins to change state at least twice in Run-Test / Idle Coffee break (from a Geek Squad add)

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