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Basic Computer

Basic Computer. The following discussions are based on a fictitious computer called “Basic Computer” by the author of the textbook It’s a much better way to learn computer architecture concepts than trying to understand the Intel Pentium architecture. Assembly Language.

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Basic Computer

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  1. Basic Computer • The following discussions are based on a fictitious computer called “Basic Computer” by the author of the textbook • It’s a much better way to learn computer architecture concepts than trying to understand the Intel Pentium architecture

  2. Assembly Language • Every computer architecture (or family of architectures) has its own unique assembly language • Unlike Java, you should not learn assembly language syntax, data types, etc. • You should learn to program/think at the assembly language level • It’s a way of thinking that requires intimate knowledge of the underlying hardware architecture

  3. Assembly Language Instructions • Each instruction has two basic parts • Operation code (opcode) • What the instruction wants the processor to do • Operand(s) (registers, memory addresses) • Data location that the instruction wants the processor to manipulated • Some operands will be explicit while others will be implicit (implied by the opcode)

  4. n-1 m+1 m 0 opcode operand/address 15 12 11 0 opcode operand/address Assembly Language Instructions • n-bit instruction format • Example – 16 bit instruction 2(n-1)-(m+1) opcodes 2(m+1) addresses 24 = 16 opcodes 212 =4096 addresses

  5. Assembly Language Instructions • Instructions within the same Assembly language may be of differing lengths • i.e. not all instructions utilize the same number of bits as we saw with the Pentium

  6. Internal Operation • To execute an assembly language instruction the processor goes through 4 steps • Fetch an instruction from memory • Decode the instruction • Read the operands from memory/registers • Execute the instruction • This is often referred to as the Fetch-Execute cycle or the Instruction cycle • To execute a program the processor repeats this cycle until a halt instruction is reached

  7. Internal Operation • All this is under the control of the Control Unit • This is the component that decodes the instruction and sends out microoperations to the rest of the hardware • The control unit can be hardwired • Made up entirely of sequential circuits designed to do precisely the fetch-execute steps – fixed instruction set • The control unit can be microprogrammed • A small programmable processor within the processor – programmable instruction set • More on this later

  8. Addressing Modes • In designing a computer architecture the designer must specify the instruction set • Opcode/operand pairs • In specifying operands there are a number of alternatives • Immediate instructions • Direct address operands • Indirect address operands

  9. Immediate Instruction • The 2nd part of the instruction is the operand (rather than the address of the operand) • An example might be an instruction that adds a constant to a register add 3 • The “3” is the value we want to add, not an address in memory

  10. Direct Address Instruction • The 2nd part of the instruction is the memory address of operand • An example might be an instruction that adds a value in memory to a register add 0x30213 • The “0x30213” is the memory address of the value that we want to add

  11. Indirect Address Instruction • The 2nd part of the instruction is the memory address of the location that holds the memory address of the operand • An example might be an instruction that adds a value in memory to a register add 0x30213 • The “0x30213” is a memory address that holds the memory address of the value that we want to add

  12. Operand Operand Operand Addressing Modes I opcode address Mode bit Immediate Direct Indirect 0 addc 3 0 add 0x33 1 add 0x33 0x33 0x33 0x42 0x42 0x42 0x88

  13. Addressing Modes • The term effective address refers to the actual address of the operand • For the previous example • Immediate address mode • Effective address is the instruction itself • Direct address mode • Effective address is the memory location 0x33 • Indirect addressing mode • Effective address is the memory location 0x42

  14. Addressing Modes • Something in the instruction word will specify which addressing mode is applicable • The operand itself (for immediate instructions) • A designated bit (for direct vs. indirect address instructions)

  15. Addressing Modes • Indirect addressing is a convenient way to implement arrays (which are nothing more than pointers to blocks of contiguous memory) • Some architectures define additional modes such as “read location then increment” • These are all derivations of the three defined here

  16. Registers • In designing a computer architecture the designer must specify the register set • There are essentially two categories • Special purpose registers • General purpose registers

  17. Special Purpose Registers • Program Counter (PC) • Holds the memory address of the next instruction of our program • Memory Address Register (AR) • Holds the address of a location in memory that we want to access (read/write) • The size of (number of bits in) these two registers is determined by the number of memory addresses in our architecture

  18. Special Purpose Registers • Instruction Register (IR) • Holds the instruction (opcode/operand) we are about to execute • Data Register (DR) • Holds the operand read from memory to be sent to the ALU • Accumulator (AC) • Holds an input to the ALU and the output from the ALU

  19. Special Purpose Registers • Input Register (INPR) • Holds data received from a specified external device • Output Register (OUTR) • Holds data to be sent to a specified external device

  20. General Purpose Registers • Temporary Register (TR) • For general usage either by our program or the architecture

  21. Registers • These registers (shown previously) are specified for the fictitious architecture given in the textbook • All architectures will have these in some form • Most architectures will have more than just these • More general purpose registers • Stack pointers • Interrupts • Program status bits • Multiple I/O ports • Timers • etc. • To effectively program the architecture (in assembly language) you need to be aware of all the available registers and their usage • High level language compilers possess this knowledge

  22. Bus • In designing a computer architecture the designer must specify the bus layout • The size of the bus (in bits) • What is connected to the bus • Access control to the bus • Recall that a bus is an efficient alternative to lots of wires when it comes to transferring data between registers, control units, and memory locations

  23. Bus Architecture S2 Access Select Memory unit 4096x16 111 S1 S0 address 001 AR 010 PC 011 16-bit Bus DR E ALU 100 AC INPR 101 IR 110 TR OUTR clock

  24. Bus Architecture • The three access select lines determine which register is allowed to write to the bus at a given time (recall that only one write at a time is allowed) • Registers have load input signals (LD) that tell them to read from the bus • If registers are smaller than the bus (less bits) than unused bits are set to 0 • Some registers have additional input signals • Increment (INR) and Clear (CLR) • See figure 5-4, page 130 of the textbook

  25. Bus Architecture • Memory has read/write input signals that tell it when to take data from the bus and send data to the bus • Memory addresses (for both read and write operations) are always specified via the Address Register (AR) • An alternative (used in many architectures) is a two bus system • One address bus • One data bus

  26. Bus Architecture • Results of all ALU (arithmetic, logic, and shift operations) are always sent to the Accumulator (AC) register • The ALU is the only way to set values into the accumulator except for the clear (CLR) and increment (INR) control lines • Inputs to the ALU come from • The Accumulator (AC) • The Data Register (DR) • The Input Register (INPR) • The E output from the ALU is the carry-out (Extended AC) bit • Many architectures pack this into a register with other status bits such as overflow

  27. Bus Architecture • Some pairs of microoperations can be performed in a single clock cycle • The key is to make sure they don’t both try to put data on the bus • Consider the RTL statement DR ← AC, AC ← DR • This is allowed since the DR ← AC microoperation uses the bus while the AC ← DR microoperation does not

  28. Instructions • We said previously that there are two parts to an instruction • Opcode • Operand • Realistically the two parts should be called • Opcode • Everything else

  29. Instructions • Three basic types • Those that reference memory operands • Those that reference register operands • Those that reference I/O devices • Again, this is only for the fictitious architecture in the textbook but you will find similar categorizations in real architectures

  30. Memory Instructions • There are 14 instructions in this class • 7 direct memory address forms • 7 indirect memory address forms 15 14 12 11 0 I opcode address I = 0 means direct memory address I = 1 means indirect memory address

  31. Memory Instructions

  32. Register Instructions • There are 12 instructions in this class • They can use the “operand field” to specify the register and type of operation since no memory address is required 15 14 12 11 0 0 1 1 1 Register operation

  33. Register Instructions

  34. Register Instructions (cont.)

  35. I/O Instructions • There are 6 instructions in this class • They can use the “operand field” to specify the exact operation since no memory address is required 15 14 12 11 0 1 1 1 1 I/O operation

  36. I/O Instructions

  37. Instruction Decoding • The control unit evaluates bits 15 – 12 to determine the instruction format • At first glance it appears that there can be only 8 unique instructions since the opcode resides in 4 bits • But, additional instructions are created through the use of the I bit an unused bits in the operand field

  38. Instruction Set Design • To be useful, an architecture’s instruction set must contain enough instructions to allow all possible computations • Four categories are necessary • Arithmetic, logical, shift operations • Moving data to/from memory from/to registers • Control such as branch and conditional checks • Input/output

  39. Instruction Set Design • The set in the book is complete in that all the possible operations on binary numbers can be performed through combinations of instructions • But, the set is very inefficient in that highly used operations require multiple instructions • This is why the Pentium instruction set is so large and complicated – it makes for efficient programs

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