Microprocessors, Advanced Partitioning an Embedded System for Multicore Design

1. Microprocessors, AdvancedPartitioning an Embedded System for Multicore Design January 31, 2012Jack Ganssle

2. The Schedule Grows Faster ThanThe Code! IBM: person-yrs LOC/month 1 439 10 220 100 110 1000 55 COCOMO: Schedule = C * KLOCM (C and M are both > 1)

3. The Productivity Crash

5. Partitioning Code Fact: The easiest way to write great modules fast is to keep them small, with few dependencies. • Smaller functions have: • fewer bugs: bug rate is 2 to 6x lower • more likely to meet specs • done faster.

6. Eye Scans

7. We Turn Micros into Mainframes 8051 - Sensors - Interface 1,000,000 lines of code

8. Complexity is not linear with LOC

9. A Better Design I/O Code I/O Code supervisory code I/O Code

10. Small and cheap

11. Interprocessor Communications Serial/Encrypt I2C – a fast serial interface Rangefinder Main CPU Transaction Processing

12. National Airport’s Radar

13. The Sergeant York

14. The Tradeoff schedule quality features

15. Feature Management

16. Requirements Scrubbing = 73.6%!

17. Don’t Wait for Hardware • Build an I/O board that plugs into the PC • Simulate! • Virtualization – Virtutech, CoWare, VaST • Fitnesse: http://fitnesse.org/ • Catsrunner: • www.agilerules.com/projects/catsrunner/index.phtml

18. What About Multicore? CPU Memory Hundreds of nsec Tens of MHz

19. Then Came Prefetchers Queue CPU Memory Under 100 nsec Tens of MHz

20. Then Came Pipelines CPU Memory 30-50 nsec Tens of MHz Old: Fetch -> Decode -> Execute Pipelined: Fetch Decode Execute

21. Cache CPU speed CPU Cache Hundreds of MHz Memory 30-50 nsec

22. Cache Splits in Two CPU speed CPU L1 Cache Over 1 GHz L2 Cache 3-5 nsec Memory 30-50 nsec

23. SMP Symmetric Multiprocessing (SMP) – multiple identical CPUs working with a shared memory array. CPU Core CPU Core Shared memory

24. Amdahl’s Law for SMP Max speedup = Where: n = Number of processors f = Percent of operation that can not be parallelized

25. With an Infinite # CPUs Speedup Portion not parallelizable

26. Best Case: 66% Parallelizable Speedup Number of cores

27. But Memory is a Bottleneck! CPU Core CPU Core L1 Cache L1 Cache Typically 32KB Shared L2 Cache Typically 2-4MB Memory

28. And so is Comm CPU Core CPU Core CPU Core CPU Core L1 Cache L1 Cache L1 Cache L1 Cache Shared L2 Cache Shared L2 Cache Memory Then there’s the cache coherency problem

29. The Irony • Programs in L1 run blazingly fast • But why use a 32 bit CPU that can • address 4 GB on a 32 KB program?

30. A Colorimeter SMP Design - Read A/D - FIFO data - Do FIR - Calculate R - Display - Read A/D - FIFO data - Do FIR - Calculate R - Display - Read A/D - FIFO data - Do FIR - Calculate R - Display A/D A/D A/D Display Display Display Core R Core G Core B Common Bus Memory

31. ASMP Asymmetric Multiprocessing (ASMP or AMP) – Multiple CPUS, identical or not, each running a specific activity CPU Core CPU Core Memory Memory Some comm link

32. The Assembly Line

33. A More Natural Design via AMP A/D FIFO FIR A/D FIFO FIR A/D FIFO FIR Calc R Display Display Display Calc G Calc B

34. Another Assembly Line CPU CPU CPU Memory Memory Memory Memory CPU Data

35. Implications Multicore can give huge performance improvements. But for non-parallel problems they may not yield much improvement. It’s hard to impossible to predict speed improvements of most algorithms once they grow larger than L1 Many embedded apps are hugely non-parallelizable. In some cases AMP offers a better solution than SMP

36. Questions?