Technology Infusion of SPACE into JPL Projects

1. Technology Infusion of SPACE into JPL Projects Jane Oh, Ph.D. Jet Propulsion Laboratory California Institute of Technology

2. Problem/Approach • Key Challenges • Increasing complexity and criticality of the FPGA (Field Programmable Gate-Arrays) devices required by today’s missions and by future missions • 32k gate devices on MER • 2M gate devices on MSL • Objectives • Improve systems engineering and assurance capability to meet mission objectives and constraints • Technology • Technology Infusion of SPACE (Software Process Assurance for Complex Electronics) into JPL Projects • Approach • Apply current software assurance techniques (e.g., inspections and peer reviews) to the FPGA logic designs • Assess the effectiveness of these assurance techniques on the FPGA logic designs • Identify any necessary improvements to these assurance techniques to be useful for the FPGA logic designs

3. SPACE Research • Point of Contact: Richard Plastow (GRC/SAIC) • Research Dates: January 2005 - December 2007 • Problem Statement • Complex electronics (such as FPGAs and ASICs) are hardware/software hybrids used across NASA in everything from wind tunnels to the International Space Station. • Previous SARP research has shown that assurance methods for these devices have not kept up with the technology. • Accomplishments • Applied software process assurance methods and techniques to complex electronics in multiple projects across three NASA Centers • Determined what techniques improve product quality and provide additional safety assurance • Made the research results available on the website http://www.hq.nasa.gov/office/codeq/software/ComplexElectronics/

4. SPACE Research Result • Can be used to assure complex electronics • at various stages of development • Comprises an overall approach that includes • document templates • techniques • checklists • Provides a guide • via a web-based interface • Assists a user • in planning the assurance process, including appropriate steps for each phase of product development

5. Process Checklists Planning Phase Assurance Planning Requirements Phase Preliminary Design Phase Detailed Design Phase Implementation Phase Testing Phase Operations Phase Maintenance or Upgrades Review Checklists Requirements review Best Practices (code reviews) Testing your design Impact Analysis Techniques Change Impact Analysis Decision Tables/Trees Design Evaluation Design Review Failure Mode and Effect Analysis (FMEA) Fault Tree Analysis Function and Physical Configuration Audits Interface Analysis Requirements Evaluation Requirements Review Risk Analysis Traceability Analysis SPACE Products

6. Technical Challenges • Things that are not covered by SPACE: • Assurance of the correctness of the FPGA designs, ESPECIALLY those aspects that are uncommon for traditional software: • Asynchronous errors (e.g., race conditions, asynchronous inputs, clock domain crossings) • Design faults (e.g., undesired or hanging states, inefficient or redundant codes) • We are seeking: • Techniques to be applied to preventing/detecting/alleviating human mistakes: • Avoiding the introduction of faults into the FPGA designs • Analyzing the FPGA designs for potential weak points and provide design options for making the system more robust • Removing faults during subsequent verification

7. THANK YOU! Q&A