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Programming Technologies, MIPT, April 7th, 2012

Programming Technologies, MIPT, April 7th, 2012. Introduction to Binary Translation Technology Roman Sokolov SMWare roman.a.sokolov@gmail.com. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012.

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Programming Technologies, MIPT, April 7th, 2012

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  1. Programming Technologies, MIPT, April 7th, 2012 Introduction to Binary Translation Technology Roman Sokolov SMWare roman.a.sokolov@gmail.com

  2. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Elbrus Binary Translation Technology for IA-32 Compatibility • Binary translation is a process of conversion of source (guest)architecture executable binary codes into executable codes of target (native) architecture. • Motivations: • binary compatibility w/o source codes recompilation (new archs enabling – more efficient, less complicated, etc.) • dynamic optimization • JIT • security • instrumentation and analysis of binaries • virtualization • simulation • …

  3. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Elbrus Binary Translation Technology for IA-32 Compatibility BT systems classes Static Dynamic Application-level DBTS Full system DBTS Guest Applications Native Applications Guest Applications Guest BIOS, OS & Libraries App level BT Native BIOS, OS & Libraries Full System BT HW HW

  4. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 native native x86 x86 x86 x86 x86 x86 guest Elbrus Binary Translation Technology for IA-32 Compatibility Example: How to use MS Windows on x86-incompatible computer x86 native Elbrus’s Approach (mode choice at boot time) Transmeta’s Approach x86 applications New native applications Intel’s Approach

  5. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) Adaptive dynamic binary translation (1/2) Adaptive retranslation Guest binaries Translations cache: execution and profiling of regions Interpretation (and profiling of traces) Non-optimizing trace translation Optimizing region translation

  6. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive dynamic binary translation (2/2): profile of execution

  7. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) BTS layout Guest Memory Space Invisible for guest programs • BT System • (native) • Memory Space • System Code • System Data • Compiler Heap • Code Caches • AddrMap Table Code Base

  8. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) Guest control transfer (AddrMap+Cache, GRAS, Native linking) AddrMapCache (H/W) AddrMap (S/W) not found Translate g. brn found Translations cache Transl. Transl. n. brn Transl. push on g. call g. call g. rtn (pop) Transl. Transl. GRAS (H/W) g.rtn (pop)

  9. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Security Self-modifying code Interrupts and precise exceptions Difference in legacy and host ops semantics Adaptive binary translation (1/2) Binary Translation Problems Memory mapped I/O devices Robust performance required!

  10. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) Hardware support

  11. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) Recovery model Optimized code Exception Handler Compensation code computes & restores context for Current RP Set Recovery Point instruction Check instr. causes exception Speculative instruction bringing exception returns diagnostic value Real exception on the same guestinstr. Back to Current RP Non-optimized code Guest Exception Handler Program execution

  12. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 0 1 0 1 0 Physical memory protection (1/2): translation Binary Translated Code Native VM Space Guest VM Space Guest code Translation Guest code Physical Space Bitmap • Physical memory space is represented via a bitmap Bitmap entry represents 4K in physical space • Translator tags guest code memory locations in the bitmap

  13. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 0 1 0 1 0 Adaptive binary translation (1/2) Physical memory protection (2/2): execution Binary Translated Code HDD TLB Native VM Space DMA Guest VM Space Exception Guest code Chipset Guest code Physical Space Bitmap Exception • Writes to the tagged memory locations result in exceptions • TLB protects tagged memory locations from CPU memory writes • Chipset protects tagged memory locations from DMA memory writes • Bitmap entries are cached internally in hardware • Exact memory address reported for each violation attempted

  14. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Dynamic optimization vs. Latency

  15. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Background optimization Approach • Optimizing translation is separated in a different thread (optimization thread), that can run simultaneously with the main execution thread. • Hot regions are detected by the execution thread and are then scheduled to be optimized in background by the optimization thread. Dual(many)-core • Optimization is moved onto underutilized processor core • Benefits • Improves application’s execution latency • Removes overhead from the application’s execution • Enables the application of more aggressive optimizations. • Single-core • Optimization is interleaved with execution • Benefits • Improves application’s execution latency

  16. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Single-core background optimization (1/3) Time-sliced optimization

  17. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Dual-core background optimization (1/2) Offloaded optimization

  18. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Future works Guest architecture multiprocessor system emulation Guest Applications Guest Applications Guest BIOS, OS & Libraries Guest BIOS, OS & Libraries Full System BT Full System BT Core0: Exec Core1: Opt HW Full System BT Core0: Exec Core1: Opt

  19. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) • Dynamic Binary Translation: summary • Key paradigm for resolving compatibility/performance • tension is speculation, recovery, and adaptive retranslation • The devil is in the details: a successful solution must deal • with unpleasant architectural details • Precise exceptions • Interrupts and DMA • Memory-mapped I/O • Self-modifying code • All techniques developed for real performance problems

  20. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Adaptive binary translation (1/2) • Dynamic Binary Translation: summary • Proc • Enables transparent transition to new architectures • Allows to transparently improve underlying hardware • Optimization of legacy codes with no sources available • Provides run-time optimization opportunities (as compared to static native compilers) • Hardware bugs masking • Cons • Translation overhead degrades runtime performance • BTS consumes RAM to store internal structures and translated codes • High-performance BT requires hardware support • Full-system BTS are hard to debug

  21. Introduction to Binary Translation Technology, Programming Technologies, MIPT, April 7th, 2012 Q&A • Further reading: Virtual Machines: Versatile Platforms for Systems and Processes by: Jim Smith, Ravi Nair; Morgan Kaufmann Publishers

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