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Multiplication 09 February 2016

CDA 3101 Spring 2016 Introduction to Computer Organization. Multiplication 09 February 2016. Multiplication. More complicated than addition Accomplished via shifting and addition Requires more time and chip area

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Multiplication 09 February 2016

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  1. CDA 3101 Spring 2016Introduction to Computer Organization Multiplication 09 February 2016

  2. Multiplication • More complicated than addition • Accomplished via shifting and addition • Requires more time and chip area • 3 versions of pencil-and-paper algorithm 0010 (multiplicand) __x_1011 (multiplier) 0010 1 -> copy & shift 0010 1 -> copy & shift 0000 0 -> shift 0010 .1 -> copy & shift 00010110 Sum Partial Products

  3. First Version (V.1) 0 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 0

  4. V.1: Hardware Multiplicand (64 bits) Shift left Multiplier (32 bits) 64-bit ALU Shift right Multiplier0 Product (64 bits) Control test Write

  5. Second Version (V.2) Product Multiplier0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 0

  6. Final Version (V.3) M u l t i p l i c a n d 3 2 b i t s 3 2 - b i t A L U C o n t r o l S h i f t r i g h t P r o d u c t t e s t W r i t e 6 4 b i t s Product 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0 10 0 0 1 1 0 1 0 0 0 0 1 1 0 1 00 0 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0

  7. Summary • Unsigned multiplication • Generate one partial product for each digit in the multiplier • Partial product = • Total product = sum of (left shifted) partial products • The multiplication of two n-bit binary integers results in a product of up to 2n bits in length 0 If multiplier digit = 0 Multiplicand If multiplier digit = 1

  8. General View 1011 Multiplicand (11) x 1101 Multiplier (13) Product (143) Multiplicand M31 . . . M0 C A Q M 0 0000 1101 1011 0 1011 1101 1011 0 0101 1110 1011 0 0010 1111 1011 0 1101 1111 1011 0 0110 1111 1011 • 0001 1111 1011 0 1000 1111 1011 Initial values Add 32-bit ALU Add Shift 1 2 Shift Shift right Control Add Shift 3 Add Shift C A31. . . A0 Q31. . .Q0 4 Multiplier

  9. Signed Arithmetic • Signed addition and subtraction • Treat operands as unsigned numbers • Use the same algorithm/hardware used for the corresponding unsigned operations Unsigned Signed 1 0 0 1 + 0 0 1 1 1 1 0 0 9 3 12 -7 3 -4 • Cannot do this for multiplication!

  10. Example Unsigned Signed 1011 x 1101 10001111 11 13 143 -5 -3 -113 • Partial solution for negative multiplicands 1001 (9) x 0011 (3) 00001001 1001 x 20 00010010 1001 x 21 00011011 (27) 1001 (-7) x 0011 (3) 11111001 (-7) x 20 = (-7) 11110010 (-7) x 21 = (-14) 11101011 (-21) • No straightforward solution if multiplier is negative

  11. Negative Multiplier • The bits of the multiplier no longer correspond to the partial products • Example: (-3) = 1101 • The partial products would be generated based on that representation of the multiplier, i.e.: • Instead, the partial products should be generated using the following powers of 2: 1: - 1 x 20 0: - 0 x 21 1: - 1 x 22 1: - 1 x 23 - 1 x 20 - 1 x 21

  12. Solution: Booth’s Algorithm  A 0, Q-1 0 M Multiplicand Q Multiplier Count n START = 10 = 01 Q0,Q-1 = 00 = 11 A A - M A A + M Arithmetic shift right: A, Q, Q-1 Count Count - 1 No Yes Count = 0 ? END

  13. Booth’s Hardware Multiplicand M31 . . . M0 Add / Subtract 32-bit ALU Control SRA A31. . . A0 Q31. . .Q0 Q-1 Multiplier

  14. Example 7 (0 1 1 1) x 3 (0 0 1 1) A Q Q-1 M 0000 00110 0111 1001 0011 0 0111 1100 10011 0111 1110 01001 0111 0101 0100 1 0111 0010 10100 0111 0001 0101 0 0111 Initial values A = A - M Shift 1 2 Shift A = A + M Shift 3 4 Shift

  15. Proof: Positive Multiplier • First, consider a simple positive multiplier 0 0 0 1 1 1 1 0 (one block of 1s surrounded by 0s) M x (0 0 0 1 1 1 1 0) = M x (24 + 23 + 22 + 21) = M x (16 + 8 + 4 + 2) = M x 30 • Notice: 2n + 2n-1 + . . . + 2n-k = 2n+1 – 2n-k => M x (0 0 0 1 1 1 1 0) = M x (25 - 21) • Both’s algorithm conforms to this scheme: • Subtracts when beginning of 1 block is found (1-0) • Adds when end of the block is encountered (0-1) • This scheme extends to any number of 1 blocks 5 4 3 2 1 0

  16. Proof: Negative Multipliers • Representation of a negative number (X): { 1 xn-2 xn-3 . . . x1 x0 } • X = -2n-1 + xn-2*2n-2 + xn-3*2n-3 . . . x0*20 • Assume the leftmost 0 is in the kth position Representation of X = { 1 1 1 … 10 Xk-1 … X0} X = -2n-1 + 2n-2 . . . 2k+1 + xk-1*2k-1 . . . x0*20 -2n-1 + 2n-2 + … + 2k+1 = -2k+1 X = -2k+1 +xk-1*2k-1 . . . x0*20 (1-0) transition occurs and a subtraction takes place

  17. MIPS Multiplication • Special purpose registers for the result (Hi, Lo) • Two multiply instructions • Mult: signed • Multu: unsigned • mflo, mfhi – move contents from Hi, Lo to general purpose registers (GPRs) • No overflow detection in hardware => Software overflow detection • Hi must be 0 for multu or the replicated sign of Lo for mult

  18. Conclusions • Multiplication => Shift-and-add • Unsigned mult = Signed mult • Booth’s Algorithm used for signed mult • MIPS has special registers (Hi,Lo) and two instructions (mult, multu) • Think about: Weekend! 

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