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The ARM7TDMI Datasheet

Outline. Part 1: The ARM ISA FeaturesPredicated InstructionPart 2: ARM Operating ModesARM State Register SetPart 3: The THUMB ISA FeaturesWhy THUMBMode switchingDifference in Registers. Part 1: The ARM ISA Features. . ARM(v4T) ISA Features. Predicated InstructionConditional InstructionFeatures rarely seen on other architecturesPC can be destination of data operating instructionsLoad/Store MultipleMultiple Operating ModesHardwired Banked Registers in each modeGeneral Purpose Regist24

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The ARM7TDMI Datasheet

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    1. The ARM7TDMI Datasheet Chapter 3: Programmer’s Model ???: ??? ijsung@csie.nctu.edu.tw 2002/7/30

    3. Part 1: The ARM ISA Features

    4. ARM(v4T) ISA Features Predicated Instruction Conditional Instruction Features rarely seen on other architectures PC can be destination of data operating instructions Load/Store Multiple Multiple Operating Modes Hardwired Banked Registers in each mode General Purpose Registers Program Status Registers Dual ISA ARM ISA mode THUMB ISA mode

    5. ARM ISA: Predicated Instruction Why predicated instruction? To eliminate conditional branch in small if-then-else Limitations? In ARM Mnemonic, condition codes are placed after instruction mnemonic Ex: “ADD” with condition “Equal” will be “ADDEQ”

    6. ARM ISA: Predicated Instruction

    7. Part 1: Summary ARM use predicated instruction to eliminate small if-then-else However, not every instruction needs to be predicated Less code density ARM make PC as legal destination of every data processing instruction Combined with load/store multiple, context switch code can be very short Very powerful but may lead to tricky assembly programming Suitable for single pipeline scalar processor Banked Register makes shorter interrupt/exception latency shorter

    8. Part 2: ARM Operating Modes

    9. ARM Operating Modes

    10. ARM Operating Modes ARM7TDMI supports seven modes of operation: User (usr): Normal ARM program execution state Class 1: Exception caused mode change Abort mode (abt): Entered after a data or instruction prefetch abort Undefined (und): Entered when an undefined instruction is executed Class 2: Interrupt caused mode change FIQ (fiq): Support a data transfer or channel process IRQ (irq): General-purpose interrupt handling Class 3: Software Interrupt Supervisor (svc): Protected mode for the operating system System (sys): A privileged user mode for the operating system

    11. ARM Operating Modes (Cont.) Mode Change: Exception: Switch to Abort or Undefined (instruction) mode Interrupts: Switch to FIQ/IRQ mode System Calls: Switch to Supervisor mode How about “System mode” ?

    12. ARM State Register Set 16+2 Addressable registers in a given mode General Purpose Registers: R0-R12 Stack Pointer: R13 Link Register: R14 PC: R15 Total 37 Registers (Bank switched) 31 General Purpose Registers 6 Status Registers Fixed Mapping Based on Processor Mode Mapping 37 registers into 17 registers Virtually every operating mode has its private: Link Register-R14 Stack Pointer-R13

    14. ARM State Register Set (Cont.)

    15. Part 2: Summary Register Banking: Make interrupt latency shorter Smaller set of program context to save Increase interrupt response Fixed “Architectural Register” to “Physical Register” Mapping based on current mode Lack of flexibility Fewer architectural register available

    16. Part 3: The THUMB ISA Mode Features

    17. THUMB Mode What is THUMB? Why THUMB? ARM/THUMB Mode Switching Differences between ARM and THUMB Modes

    18. Thumb Mode: What is Thumb? ??? Thumb ISA: 16-bit instruction, dynamically decompressed into ARM Instruction before execution Fewer directly accessible GPRs (Only R0-R8) The CPU can be switched between ARM ISA mode and Thumb ISA mode dynamically

    19. Thumb Mode: What is Thumb?

    20. The Thumb Mode: Why Thumb? Addresses higher code density by packing common instructions into 16-bit Reduces bus width and activities Datapath remain unchanged, thus still 32-bit In an typical application, performance-sensitive code can be in ARM ISA, while other code in Thumb Denser code, less performance impact

    21. ARM/THUMB Mode switch Switch to ARM ISA mode automatically on exception Can also be switch by BX (Branch and Exchange) Instruction Note: gcc-3.X now have support for “ARM/Thumb inter-working” (Unsupported in 2.9x)

    22. Thumb/ARM differences Most Thumb instructions are unconditional ALL ARM instructions are conditional Many Thumb data processing instructions use a 2-address format ARM data processing instructions use a 3-address format Thumb Instructions are less regular than ARM Instructions For higher code density

    23. Part 3: Summary Thumb: Try to make higher code density Thumb use a “decompressor” to decode 16-bit Thumb instruction into 32-bit ARM instruction in the decode stage Adding Thumb support does not change original ARM datapath (except for the Thumb decompressor) Thumb: 16-bit, non-predicated ISA

    24. ??????, ???? References: Furber, ARM System-on-Chip Architecture ARM Architecture Reference Manual The ARM7TDMI Datasheet Chapter 3.

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