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Applied VLSI Design

The third design of Robert Gubitz. Applied VLSI Design . Stage 2 design. Changes since Stage 2. Replace the remaining Carry-Save-Array multipliers with Wallace Tree multipliers Use term sharing for the multipliers Replace Ripple-Carry adders with Carry-Skip look-ahead adders

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Applied VLSI Design

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  1. The third design of Robert Gubitz Applied VLSI Design

  2. Stage 2 design

  3. Changes since Stage 2 • Replace the remaining Carry-Save-Array multipliers with Wallace Tree multipliers • Use term sharing for the multipliers • Replace Ripple-Carry adders with Carry-Skip look-ahead adders • Added additional pipeline stages

  4. Term Sharing Y: • 001001_10010001_01101001 • 010010_11001000_10110100 • 000011_10100101_11100011 • Cb: • 000101_01100110_01001001 • 001010_10011001_10110111 • 001111_11111111_11111111 – replaced with shifter • Cr: • 001111_11111111_11111111 -- replaced with shifter • 001101_01100101_11100100 • 000010_10011010_00011100 Precalculate coefficient*color and share between multipliers

  5. Carry-Skip-Lookahead-Adder • Ripple-Carry adders work only for FPGA  replacement with faster adders • combination of look-ahead and skip-logic

  6. Resulting Design

  7. Finding Sweet-Spot • Adjust desired leakage power to very low value • Synthesize for multiple frequencies and make a diagram to find metric‘s theoretical sweet spot Sweet-Spot

  8. Results – Synthesis

  9. Thank YOU For YOUR ATTENTION

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