Test structures for the evaluation of TowerJazz 180 nm CMOS Imaging Sensor technology

1. ALICE ITS microelectronics team - CERN Test structures for the evaluation of TowerJazz180 nm CMOS Imaging Sensor technology

2. TID_TJ180 layout Tower Jazz 0.18 um CMOS Imaging Sensor 3.7 mm 2.2 mm CMOS test structures with Deep p-well CMOS test structures Breakdown diodes ALICE ITS microelectronics team - CERN

3. CMOS test structures 125 μm Block A Block B Block C Block D 167 μm, 100 μm, 167 μm, 125 μm, 167 μm, 100 μm, 167 μm 1.2 mm 2.0 mm 125 μm horizontal pitch 100 μm, 125 μm, 167 μm vertical pitch 16 x 8 pad matrix = 128 pads Pad opening size: 76 μm x 76 μm Each block has an individual power supply and it can be tested individually. ALICE ITS microelectronics team - CERN

4. MOS devices * Low Vt transistors cannot be used in a design with High Vt transistors • 78 MOS with different sizes and tox and Vth options Layout examples Enclosed Layout NMOS NMOS PMOS NMOS in a Triple Well (Deep N-Well) for P-well isolation and noise immunity 1 mm ALICE ITS microelectronics team - CERN

5. MOS test structures arrays Array Purpose ALICE ITS microelectronics team - CERN

6. Other devices ALICE ITS microelectronics team - CERN

7. Breakdown diodes Cross section nwell diode p+ : -30 V; n+ : 0 V depleted volume nwell with deep pwell in the between Measurements: Breakdown voltage and depletion layer capacitance depleted volume NW width: 1 µm or 2 µm NW with DPW width: up to 3.40 µm ALICE ITS microelectronics team - CERN

8. Single Event Effects evaluation test chip ALICE_ITS_TJ180_T1 • SP RAM: 16 macro blocks, 1024 x 16 bit • DP RAM: 8 macro blocks, 2048 x 16 bit • 16 bit 32 K stages D-Flip-Flopshift register ALICE ITS microelectronics team - CERN

9. SEU_TJ180 layout 4872 µm SP_RAM 4454 µm Shift Register DP_RAM ALICE ITS microelectronics team - CERN