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Chapter 2 Introduction to Finite State Machine

Chapter 2 Introduction to Finite State Machine. Introduction. FSM(Finite State Machine) A tool to model the desired behavior of a sequential system A FSM consists of several states. Inputs to the machine are combined with the current state to determine the next state.

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Chapter 2 Introduction to Finite State Machine

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  1. Chapter 2 Introduction to Finite State Machine

  2. Introduction • FSM(Finite State Machine) • A tool to model the desired behavior of a sequential system • A FSM consists of several states. • Inputs to the machine are combined with the current state to determine the next state. • Outputs are generated based on either the state of the machine, or the state of the machine and machine inputs.

  3. Figure 2.1 State machine models

  4. 2.1 State Diagram and State Table • State diagrams and state tables • Convenient mechanism for specifying the behavior of sequential systems. • Table 2.1 shows the state tables the alarm clock example. • Figure 2.2 shows the state diagram for the alarm clock example. • Each state is represented by a circled vertex. • Mutually exclusive: No input values should meet the conditions of more than one arc. • Self-arcs

  5. Figure 2.2 State diagram for the alarm clock example

  6. Figure 2.3 The state diagram for the table 2.2

  7. 2.2 Mealy and Moore Machines • A finite state machine can be represent outputs in one of two ways. • Moore machine (Figure 2.2 (a) ) • Mealy machine (Figure 2.2 (b) ) • Notice that the self-arcs must be shown for the Mealy machines, but not for Moore machines.

  8. Figure 2.4 JK flip-flop with modified outputs: Table 2.2 (b)

  9. 2.3 Designing State Diagrams • Modulo 6 counter • String checker • Toll booth controller

  10. Modulo 6 counter • Modulo 6 counter • 000001010011100101000 • Table 2.3

  11. Figure 2.5 (a) State diagram for the modulo 6 counter: Mealy

  12. Figure 2.5 (b) State diagram for the modulo 6 counter: Moore

  13. String Checker • A string checker inputs a string of bits, one bit per clock cycle. • When the previous three bits form the pattern 110, it sets output M=1; otherwise M=0 • Refer to Table 2.4 and Figure 2.6

  14. Figure 2.6 State diagrams for the string checker: (a) Mealy (b)Moore

  15. Figure 2.A State Diagram for the string checker with revised state assignment

  16. Toll Booth Controller • A toll booth controller has two external sensors. • Whether a car is at the toll booth • C=1 when a car is present • Whether a coin has been deposited in the toll booth’s collection basket and its value • I0I1=00 : no coins I0I1=01 : a nickel • I0I1=10 : a dime I0I1=00 : a quarter • This toll booth does not accept pennies nor coins with values above 25 cents. • Two output lights and one alarm • R • G • A

  17. Figure 2.7 State diagram for the Moore machine for the toll booth controller

  18. 2.4 From State Diagram to Implementation • Assigning the state values • Mealy and Moore machine implementation • Generating the next states • Generating system outputs • An alternative design

  19. Assigning the state values • Each state must be assigned a unique binary value. • For a machine with n state, the state value will have log2 n bits. • Although any values can be assigned to the states, some assignments are better than others

  20. Figure 2.8 (a) Mealy

  21. Figure 2.8 (b) Moore

  22. Mealy and Moore machine implementation • The generic Mealy machine implementation: Figure 2.9 • The generic Moore machine implementation: Figure 2.10

  23. Figure 2.9 (a) Generic Mealy Machine

  24. Figure 2.9 (b) Generic Mealy Machine’s implementation

  25. Figure 2.10 (a) Generic Moore Machine

  26. Figure 2.10 (b) Generic Moore Machine’s implementation

  27. Generating the next states • Table 2.7 shows the truth table needed for the modulo 6 counter.

  28. Figure 2.11 K-map for the next state of the modulo 6 counter

  29. Figure 2.12 Implementation of the next state logic for the modulo 6 counter

  30. Figure 2.13 Primary implementation of the next state logic for the modulo 6 counter using a multiplexer Refer to Table 2.8

  31. Figure 2.14 Final implementation of the next state logic for the modulo 6 counter using a multiplexer

  32. Figure 2.15 Implementation of the next state logic for the modulo 6 counter using a lookup ROM

  33. Generating system outputs • Table 2.9 shows the tables for the Mealy and Moore machines for the modulo 6 counter.

  34. Figure 2.16 Mealy machine implementation of the modulo 6 counter

  35. Figure 2.17 Moore machine implementation of the modulo 6 counter

  36. Figure 2.18 (a) Moore machine implementation of the modulo 6 counter using a lookup ROM

  37. Figure 2.18 (b) Data

  38. An alternative design • There are other methods of implementing finite state machines.

  39. Figure 2.19 (a) Alternative state machine hardware design: generic hardware

  40. Figure 2.19 (b) Moore machine implementation of the modulo 6 counter

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