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习 题 解 析

习 题 解 析. 助教：谢 萍 2007.10.24. 2.1.

jeremy-potts
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习 题 解 析

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  1. 习 题 解 析 助教：谢 萍 2007.10.24

  2. 2.1 • Let A＝A(1)，A(2)，…，(1000) and B：B(1)，B(2)，…，B(1000) be two vectors(one dimensional arrays) comprising 1000 numbers each that are to be added to form an array C such that C(I)＝A(I)+ B(I) for I＝1，2，…，1000 using IAS instruction set, write a program for this problem.

  3. 2.1 Reference answer • Memory addresscontents 1 A(1) 2 A(2) … … 1000 A(1000) 1001 B(1) … … 2000 B(1000) 2001 C(1) … … 3000 C(1000)

  4. Memory address contents 3001 999 3002 1 … … 3100 JUMP M(3100,20:39) LOAD M(1) 3101 JUMP M(3101,20:39) ADD M(1001) 3002 JUMP M(3102,20:39) STOR M(2001) 3103 LOAD M(3100) ADD M(3002) 3104 STOR M(3100) LOAD M(3101) 3105 ADD M (3002) STOR M(3101)

  5. Memory address contents 3106 LOAD M(3102) ADD M(3002) 3107 STOR M(3102) LOAD M(3001) 3108 SUB M(3002) STOR M(3001) 3109 JUMP M(3100,0:19)

  6. 3.2 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: The first byte contains the opcode and the remainder the immediate operand or an operand address. • a. what is the maximum directly addressable memory capacity (in bytes)? • Reference answer: The maximum directly addressable memory capacity is 224bytes. 0 7 31

  7. 3.2 • b. Discuss the impact on the system speed if the microprocessor bus has • a 32-bit local address bus and a 16-bit local data bus, or • a 16-bit local address bus and a 16-bit local data bus. • Reference answer: • If system address is 32-bit, an operand address is only 24-bit. The other mechanism is required to provide 32-bit address, so more time takes to achieve the corresponding address. • If system address is 16-bit , the instruction can provide the address directly.

  8. 3.2 • C. How many bits are needed for the program counter and the instruction register? • Reference answer: • The length of PC is usually same to the length of word, so 32 bits are needed for the program counter • The length of IR is usually same to the length of instruction, so 32 bits are needed for the instruction register.

  9. Ex. 3.2 • 指令中地址字段24比特，故可直接寻址224Byte • （1）系统32位地址，而指令中只提供24位地址，因此必须设立至少8比特的页面寄存器，或应当像8086系统一样设立段寄存器才能一次提供32位地址；否则就要输出2次才能传输完地址 （2）系统只16位地址，而指令可提供24位地址，因此一次就可提供。[此问题答案可以灵活] • 程序计数器PC宽度一般与字长相同，这里为32比特；指令寄存器宽度应当与指令长度相同，这里为32比特。

  10. 4.4 • Suppose an 8-bit data word stored in memory is 11000010. Using hamming algorithm, determine what check bits would be stored in memory with the data word. Show how you got your answer.

  11. Answer: C8 C4 C2 C1 C1=M1⊕M2⊕M4⊕M5⊕M7=0⊕1⊕0⊕0⊕1=0 C2=M1⊕M3⊕M4⊕M6⊕M7=0⊕0⊕0⊕0⊕1=1 C4=M2⊕M3⊕M4⊕M8 =1⊕0⊕0⊕1 =0 C8=M5⊕M6⊕M7⊕M8 =0⊕0⊕1⊕1 =0 Result:

  12. 4.6 • How many check bits are needed if the Hamming error correction code is used to detect single bit errors in a 1024-bit data word? • Answer: According to the formula ∴

  13. 4.7 • Develop an SEC code for a 16-bits data word. Generate the code for the data word 0101000000111001. Show that the code will correctly identify an error in data bit 4.

  14. 4.7 Answer: (M4)

  15. 4.8 • A set associative cache consists of 64 lines divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.

  16. 4.8 Answer: 27=128, 64/4=16=24, 4k*128=212*27=219 19-7-4=8

  17. Answer: • The total memory space 4k * 128(212 * 27=219) bytes, 19 bits needed • 64/4=16(24) sets, 4 bits needed. • 128words (27) each block , 7 bits needed. • 19-4-7=8 bits tag field used

  18. 4.20 • Consider a memory system with the following parameters: Tc=100ns Cc=0.01cents/bit Tm=1,200ns Cm=0.001cents/bit • What is the cost of 1Mbyte of main memory? • What is the cost of 1Mbyte of main memory using cache memory technology? • If the effective access time is 10%greater than the cache access time, what is the hit ratio H?

  19. 4.20 Reference answer • a. The cost of 1M byte of main memory is: 1M byte * 8 bits /byte * 0.001 cents/bit = 8388.608 cents • b. The cost of 1M byte of cache memory is: 1M byte * 8 bits/byte * 0.01 cents/bit = 83886.08 cents • c. HTc+(1-H)(Tm+Tc)=(1+10%) Tc ∴ H=99.17% • Note: • 1M * 8 * 0.001 = 223 * 0.001 = 220 (0.001=10-3)

  20. 5.4 • What is the transfer rate for a nine-track magnetic tape unit whose tape speed is 120 inches per second and whose tape density is 1,600 linear bits per inch?

  21. 5.4 • Conditions available: • nine-tracked • the tape speed 120 inches/second • the tape density 1600 linear bits/inch • What is the transfer rate? • Answer: 120 inches/s * 1600 linear bits/inch * 9 =1728000 bits/s

  22. 5.5 • Assume a 2400-foot tape reel; nine-tracked; an interrecord gap of 0.6 inch where the tape stops midway, between reads; that the rate of tape speed increase/decrease during gaps is linear; that the tape speed is 120 inches per second; and that the tape density is 1,600 linear bits per inch. Data on the tape are organized in physical records, where each physical record contains a fix number of user-defined units, called logical records.

  23. 5.5 • conditions available: • the tape is 2400-foot long • 1 food=12 inch • have nine-tracked • length of an interrecord gap is 0.6 inch • the tape speed is 120 inches/second • the tape density is 1600 linear bits/inch. • data on the tape are organized in physical records, which are formed by N logical records.

  24. 5.5 • a. How long will it take to read a full tape of 120-byte logical records blocked 10 per physical record? • Answer: 1food=12inches The tape speed during gap is 60 inch /second The length of a physical record excluding its following gap is: 120 * 10 * 8 ÷1600 = 6 inch The physical records and gaps individually are 2400 * 12/(6＋0.6)≈4363 So the total time to read the full tape is : 4363 * (6÷120＋0.6÷60)≈261.78 seconds

  25. 5.5 • b. How long will it take to read a full tape of 120-byte logical records blocked 30 per physical record? • Answer: The length of a physical record excluding its following gap is: 120 * 30 * 8 ÷1600 = 18 inch The physical records and gaps individually are: 2400 * 12/(18＋0.6)≈1548 So the total time to read the full tape is : 1548 * (18÷120＋0.6÷60)≈247.68 seconds

  26. 5.5 • c. How many logical records will the tape hold with each of the preceding blocking factors? • Answer: (1) (2400*12)/(6 +0.6)*10=4363 (2) (2400*12)/(18+0.6)*30=1548*30=46440 • d. What is the effective overall transfer rate for each of the two preceding blocking factors? • Answer: (1) (120*10)/(6/120+0.6/60) = 20000(byte/s) (2) (120*30)/(18/120+0.6/60) = 22500(byte/s)

  27. e. What is the capacity of the tape? • Answer: a.(2400*12)/(6+0.6)*10*120=25600000(byte) b.(2400*12)/(18+0.6)*30*120=36378947(byte)

  28. Question & Answer

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