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MICE Readout DFPGA Firmware Progress

MICE Readout DFPGA Firmware Progress. Done  2xTrip-t  DFPGA  AFPGA (single channel) Schematic simulated correctly with static data. Discriminator bit map transfer control blocks interfaced to Xilinx Core Generated components

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MICE Readout DFPGA Firmware Progress

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  1. MICE Readout DFPGA Firmware Progress Done  2xTrip-t  DFPGA  AFPGA (single channel) Schematic simulated correctly with static data. Discriminator bit map transfer control blocks interfaced to Xilinx Core Generated components Reading Trip-t Discriminator Bit map into DFPGA MapFIFOs with Depth control Down loading the Discriminator Bit map into Df-Af interface FIFO on Digitise Raise Busy to Collector FPGA FWFT control LVCMOS2 logic I/O used. (Incompatible with LVTTL .. KB to monitor) Software problems! Underway  Trip-t  DFPGA  AFPGA Schematic simulation with dynamic data. Next  Add pin configuration Simulate  Test  Implement L1 Data Readout

  2. DFPGA Schematic (Df->Af single channel)

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