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Function-Architecture Co-design

Function-Architecture Co-design. Function-Architecture Co-design. The essence of function/architecture codesign methodology Capture and iterate heterogeneous system behavior, both dataflow and control Compose behavior by linking them with discrete event semantics

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Function-Architecture Co-design

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  1. Function-Architecture Co-design

  2. Function-Architecture Co-design • The essence of function/architecture codesign methodology • Capture and iterate heterogeneous system behavior, both dataflow and control • Compose behavior by linking them with discrete event semantics • Capture a minimal or relaxed product architecture

  3. Function-Architecture Co-design: Cadence Approach

  4. Function

  5. Architecture

  6. Function to Architecture Mapping

  7. Virtual Component Interface • Goal • Maximum portability • No requirements of modification of VCs. • Assumption • Initiator/Target connection(point-to-point connection) • Peripheral VCI • Basic VCI • Advanced VCI

  8. VCI characterization Request and response protocol

  9. Peripheral VCI

  10. PVCI protocol • Operation Type • Read8, Read16, Read32, Read N cells • Write8, Write16, Write32, Write N cells • Handshake protocol

  11. Basic VCI

  12. Basic VCI • Cell, packet, packet chain • Command, i.e. transaction • NOP (optional), Read, Write, Locked-Read(optional) • Addressing Mode • Random address mode • Contiguous mode • Wrap mode • Constant

  13. BVCI READ and WRITE operation

  14. Packet Chain Transfer

  15. Advanced VCI • An Optimal extension of BVCI for multi-processor SoC • Incompatibility with BVIC • Out-of-order transfer • Advanced packet model • Protocol • Advanced packet model • Multi-thread transaction • Out-order transfer • Arbitration hide mode

  16. Advanced Packet Model

  17. Out-of-order transfer

  18. Arbitration Hide Mode

  19. Q3: Dynamic Power Management in On-Chip Communication?Not yet, but … • Techniques of on-chip communication power reduction • Encoding/decoding relationship • E.g. Bus invert coding, … • Reducing voltage swing (diff. signaling)

  20. Recent work by Prof. De Micheli • On-chip bus error rate v.s. average energy/useful bit • Error sources • Crosstalk, EMI, timing errors, soft errors

  21. Advanced Bus Architecture:Error-resilient Coding • Error-detection code or error-correction code • Energy trade-off between • Retransmission • Error-correction coder/decoder

  22. Energy Issue in On-chip Bus Arbitration • Centralized bus arbitration • As bus scale grows up, energy inefficient • Energy cost of communicating with the arbiter and the arbiter complexity grows up more than linearly. • Distributed bus arbitration • Code division multiple access (ISSCC’00) • Just began to consider this problem.

  23. Low-Power Bus Topology Design: Pedram, DATE00 • Single bus? • Split two buses? Which one consumes less bus power?

  24. Manual work is possible in func/arch codesign flow? • Manual work in the flow • Practically, always necessary to optimize system performance or minimize the cost. • Vendor dependent situation • At least, after manual optimization • Validation by simulation may be possible.

  25. Transaction and Transfer in VCI • Explained in VCI

  26. Newly designed VC and Wrapper Latency

  27. Bus Architectures and Their Performance Comparison • Bus architectures • PCI, AMBA, Pentium • Others: CoreConnect, PI bus • VCI specification • Most of useful bus functions are included. • Benchmark reports

  28. Little/Big EndianCost & Performance • To convert them, • A barrel shifter type converter will be enough.

  29. Pros and Cons:Bus versus Network

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