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Practical Strategies for Power-Efficient Computing Technologies

Practical Strategies for Power-Efficient Computing Technologies. Karim Al-Sheraidah December 8 th 2011. Overview. Survey of Power reduction techniques ~8x improvement in power efficiency No performance lose Voltage Scaling Optimum VDD = 0.5 V IBM Blue Gene system. Introduction.

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Practical Strategies for Power-Efficient Computing Technologies

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  1. Practical Strategies forPower-Efficient ComputingTechnologies Karim Al-Sheraidah December 8th 2011

  2. Overview • Survey of Power reduction techniques • ~8x improvement in power efficiency • No performance lose • Voltage Scaling • Optimum VDD = 0.5V • IBM Blue Gene system

  3. Introduction • The Regime of interest

  4. Introduction cont… Pactive = Ceff V2 ƒ + Ileak V Ceff is V dependent  Ceff V2 ∞ V2.5 ƒ is linearly V dependent  ƒ = α(V – V0) V0 ≈ 0.25V Pactive = αCeff V2 (V – V0) + Ileak V ∞ V3

  5. The Case for Voltage Scaling Departing from scaling theory

  6. The Case for Voltage Scaling Optimum VDD = 0.5v

  7. The Case for Voltage Scaling cont… Optimum VDD = 0.5v

  8. Enablement (1) Operating Margin improvement

  9. Enablement (2) Low variability devices ET-SOI Fin-FET

  10. Enablement (3) Digital Noise Resistive: dVR/VDD = IR/VDD ∞ ( VDD – VT)1.5/VDD Capacitive: dVC/VDD = [CaggVDD/(Cagg + Cvic)]/VDD = Cagg/(Cagg + Cvic) Inductive: dVL/VDD = [ L ∂I/∂t ]/VDD ∞ (L I)/(VDDҭ) ∞ (VDD – V0)( VDD – VT)1.5/VDD

  11. Enablement (4) On-Chip Power System

  12. Case study (IBM Blue Gene) • Top500 HPC from 2004 to 2007 • Operating at 850MHz • Performance of up to 13.9Tflop • 4096 parallel processor cores • - Three chip voltage bins

  13. Conclusion • Power efficiency through voltage scaling. • Optimum VDD = 0.5v. • lowering of variability. • Increasing margin. • Massive parallelism. • High integration.

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