FFT Final Presentation

1. FFTFinal Presentation

2. Project definition • Developing FFT component for wireless communication system

3. Project stages • Algorithm calculating • Software Debugger Application (Excel) • HPADS Fixed-point design • RTL (Verilog) • Testing

4. FFT---Basic requirements • 128/32 input sequence length • Direct/Inverse modes of Transformation • Quadrature Phase Windowing for convolution • Various Serial I/O feeding modes • 8bit input precision • 40 MHz clock • 65 clock cycles for FFT-128 operation • 10 clock cycles for FFT-32 operation • 19 clock cycles for FWI-32 operation

5. FFT control tasks • Task FFT Clear – Zeroing reset of Input buffers (16 clock cycles). • Task Kill --Synchronous system termination and reset (1 clock cycle).

6. FFT 128 • Split Radix • 3 stages Radix 4 • 1 stage Radix 2 (combined with last Radix4) • In Place Computation • Separated resources Input feeding Computational operation Output streaming **Support Back to Back input feeding

7. FFT-128 Data path • 128

8. FFT modes of operation • FFT-128 • FFT-32 Implemented as 3 last stages of FFT-128 algorithm (2*Radix-4 and Radix-2) • Inverse FFT Implemented by Interchange of Real/Image Inputs and Interchange of Real/Image Outputs • FWI-32 correlation mode - direct FFT-32 - window with programmable quadrature phase pattern -inverse IFFT-32

9. FWI-32 Data path • 32

10. FFT 128 • Memory Allocation

11. Clock Count per stage • .

12. FFT Cell-Count • Resources • 2 Radix-2 Butterflies • 6 complex multipliers • 4 Radix-2 Butterflies • 8 FirstRAMs • 8 Operational RAMs • 8 LastRAMs • Twiddle Factors’ ROM • Algorithm controller

13. Algorithm development • HPADS

14. FFT Block Diagram • Top Level

15. Arithmetic unit • 4 Arithmetic blocks consequently implementing FFT stages ·2 parallel Radix-4 Butterfly operations ·6 parallel 12 bit width Radix-4 Complex multipliers ·4 parallel Radix-2 Butterfly operations ·8 Quadrature phase multipliers .

16. Memory/Data path unit • Data path set of RAM arrays and data routing MUXes • ·Input feeding storage FirstRAM : 8 Dual port RAMs 16x16 • ·Operating data storage OpRAM : 8 Dual port RAMs 16x24 • ·Output storage buffer LastRAM : 8 Dual port RAMs 16x20 • ·Output FWI storage buffer LastFwiRAM : 8 Dual port RAMs 4x20

17. Twiddle factors ROM unit • Block description This block supplies complex twiddle factors values for multiply operation of Radix-4 Butterfly. Implemented with Look-Up-Table due to big redundancy in harmonic data.

18. Control unit • a

19. Control unit functions • Data path and Memory Controller • Address generator • RAM to Butterflies routing • Butterflies to RAM routing • Real and Image Combining/Splitting Storage • Arithmetic unit Controller • Management of FFT interface in various operation modes and tasks

20. FFT Interface operation • Ptam_fft_mode [1:0] should be asserted at least one clock cycle before input data valid . •  Serial input data stream ptam_fft_data_in_I[7:0] and ptam_fft_data_in_q[7:0] should be enveloped by Input valid ptam_fft_wr signal ** Support Back to Back operation •  Serial output data stream pfft_data_out_I[7:0] and pfft_data_out_q[7:0] is enveloped by Output valid pfft_out_valid signal •  Serial output FWI data stream pfft_datafwi_out_I[7:0] and pfft_datafwi_out_q[7:0] is enveloped by Output valid pfft_outfwi_valid signal •  As Ptam_task fft_clear pulse is detected ,16 Clock cycle Zeroing of FirstRAM is performed . • Pfft_clear_done pulse is asserted at 16th clock cycle after ptam_task fft_clear pulse • As Ptam_task kill pulse is detected ,1 Clock cycle Reset of all FFT block is performed .

21. IFFT-128 operation • IFFT

22. FFT-128 operation • FFT

23. FWI-32 operation • FWI

24. Quality criteria Testing Requirement: • Total Harmonic Distortion (>55dB) Signal to Noise Ratio of FFT Output sequence • Spurious Free Dynamic Range (>40 dB) Testing Direct and Inverse Harmonic waves transformation Performed with 8 width bit Input 12 width bit Calculating precision 10 width bit Output THD = 74dB SFDR = 50dB