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Ch. 9 Counters and Shift Registers

Ch. 9 Counters and Shift Registers. 이 상 훈 경남대학교 전기전자공학부. 단원목차. 9.1 Basic Concepts of Digital Counters 9.2 Synchronous Counters 9.3 Design of Synchronous Counters 9.4 Programming Binary Counters in VHDL 9.5 Control Options for Synchronous Counters

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Ch. 9 Counters and Shift Registers

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  1. Ch. 9Counters and Shift Registers 이 상 훈 경남대학교 전기전자공학부

  2. 단원목차 9.1 Basic Concepts of Digital Counters 9.2 Synchronous Counters 9.3 Design of Synchronous Counters 9.4 Programming Binary Counters in VHDL 9.5 Control Options for Synchronous Counters 9.6 Programming Presettable and Bidirectional Counters in VHDL 9.7 Shift Registers 9.8 Programming Shift Registers in VHDL 9.9 Shift Register Counters

  3. Counter Terms • Counter: A Sequential Circuit that counts pulses. • Uses: Event Counting, Frequency Division, Timing and Control Operations. • Shift Register: A Sequential Circuit that moves stored data bits in a specific direction. Used in Serial Data Transfers, SIPO/PISO Conversions, Arithmetic, and Delays. • A Counter is a digital circuit whose outputs progress in a predictable repeating pattern, it advances on state for each clock pulse. • State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter.

  4. Counter Modulus • Modulus of a counter is the number of states a counter sequences through before repeating(mod-N). • A Mod-12 Up Counter counts 12 States from 0000 to 1011 (0 to 11) and the repeats. • A Mod-12 Down Counter counts 12 States from 1011 to 0000 (11 to 0) and the repeats.

  5. Counter State Diagram Figure 9.2

  6. Truncated Counters • A N-Bit Counter that counts the maximum modulus (2N) is called a Full Sequence Counter such as Mod-2, Mod-4, Mod-8 etc. • A N-Bit Counter whose modulus is less than the maximum possible is called a Truncated Sequence Counter such as Mod-3 (N=2), Mod-12 (N=4). • A Mod-12 Counter counts up from 0000 to 1011 while a Mod-16 counts up from 0000 to 1111. Both counters are 4-Bit (N=4).

  7. Timing Diagrams • The outputs (Q0  Q3) of the counter can be used as frequency dividers with Q0 = Clock  2, Q1 = Clock  4, Q2 = Clock  8, and Q3 = Clock  16. Figure 9.4

  8. Synchronous Counter Fig. 9.8 Synchronous Counter Block Diagram Direct the counter to its next state Keep the present state

  9. Synchronous Counter Design • Draw a state diagram showing state changes, and inputs and outputs. • Create a Present/Next State Table. • List Present States in Binary Order and Next States based on the State Diagram. • Use FF Excitation Tables to determine FF (JK,D,T) inputs for each Present  Next State Transition. • Specify Inputs Equations for each input and simplify using Boolean Reductions. • This can be a long tedious process. • A VHDL design for counters is more easily done and not as time consuming.

  10. Synchronous Counter Design (Example 9.5) Fig. 9.18

  11. D3 = /Q3Q2Q1Q0 + Q3/Q2 + Q3/Q1 + Q3/Q0 = /Q3Q2Q1Q0 + Q3(/Q2 + /Q1 + /Q0) = /Q3Q2Q1Q0 + Q3/(Q2Q1Q0) = Q3 XOR Q2Q1Q0 D2 = /Q2Q1Q0 + Q2/Q1 + Q2/Q0 = /Q2Q1Q0 + Q2(/Q1 + /Q0) = /Q2Q1Q0 + Q2/(Q1Q0) = Q2 XOR Q1Q0 D1 = Q1/Q0 + /Q1Q0 = Q1 XOR Q0 D0 = /Q0 = Q0 XOR 1

  12. Programming Binary Counter in VHDL • Sequential Counters use a Process Statement to control transitions to the next count state. • A VHDL Attribute is used with an identifier (signal) is used to define clock edges. • Clock uses an Attribute called EVENT such as (clk’EVENT AND clk=‘1) to define a Rising Edge Clock Event. • INPUTS ACTION • RESET=1 CLK=1 CLK’event • FALSE FALSE FALSE Unspecified • FALSE FALSE TRUE Unspecified • FALSE TRUE FALSE Unspecified • FALSE TRUE TRUE Q <= D • TRUE - - Q <= ‘0’

  13. Behavioral Description of Counters I • Basic Entity for Binary Counter with Asynchronous Clear. ENTITY ct_simp IS PORT( clk, clear : IN BIT; q : OUT INTEGER Range 0 to 255); END ct_simp; -- Counter Outputs (8 Bit) are given as an integer with a -- range of 0 to 255 (Full Sequence Counter)

  14. ARCHITECTURE a OF ct_simp IS BEGIN PROCESS(clk, clear) VARIABLE count : INTEGER RANGE 0 to 255; BEGIN IF(clear = ‘0’) THEN count := 0; ELSE IF(clk’EVENT AND clk = ‘1’) THEN count := count + 1; -- integer(no quote) END IF; END IF; q <= count; END PROCESS; END a;

  15. Behavioral Description of Counters II • The process was set to execute on changes in clk or clear. • The asynchronous clear is placed before the clk EVENT. • The clk attribute (EVENT) was set for rising edge. • The next state transition was controlled by a simple integer addition (count := count +1). • This same approach could be used by other hardware (multipliers, dividers etc.). • In the example a Variable count was used for the integer operations(the increment). • It uses a Variable Assignment Operator (:=) instead of a Signal Assignment (<=).

  16. LPM Counters I • The Altera LPM(Library of Parameterized Modules) Counter can be used to create counter designs in VHDL. • This is a Structured Design Approach that uses the LPM-Counter as a Component in a Hierarchy. • The LPM Counter is instantiated in the Structured Design. • The basic parameters of the LPM Counter such as width are defined with a Generic Map. • The Port Map is used to connect LPM Counter I/O to the actual VHDL Design Entity.

  17. VHDL LPM Library Declaration and Entity • In this case we add the Altera LPM Library to the usual STD_LOGIC. • The ieee library must be declared before the LPM library. • LIBRARY ieee; • USE ieee.std_logic_1164.ALL; • LIBRARY LPM • USE lpm.lpm_components.ALL; • Entity for an 8-Bit Mod-256 Counter. LPM requires the use of STD_LOGIC data types. • ENTITY lpm_simp IS • PORT( clk, clear : IN STD_LOGIC; • q : OUT STD_LOGIC_VECTOR(7 downto 0)); • END lpm_simp;

  18. VHDL LPM Architecture I • The Architecture uses a Generalized LPM counter with a width set to 8 Bits and mapping clk, clear and q to the IO of LPM. • In this case we do not need any integer expression for the counts, process to control clk or asynchronous. They are mapped to a programmable width counter. • _instance_name : _component_name • GENERIC MAP (_parameter_name => _parameter_value, • _parameter_name => _parameter_value) • PORT MAP (_component_port => _connect_port, • _component_port => _connect_port); • -- component name : LPM component name • -- parameter name : name defined in LPM component • -- component port : LPM port name • -- connect port : name declared in the entity or as signals or variables

  19. VHDL LPM Architecture II ARCHITECTURE count OF lpm_simp IS SIGNAL clrn : STD_LOGIC; -- Clear for LPM BEGIN count8 : lpm_counter GENERIC MAP(LPM_WIDTH => 8) PORT MAP(clock => clk, aclr => clrn, q => q(7 downto 0)); clrn <= NOT clear; END count;

  20. Control Options for Synchronous Counters • Parallel Load: A function (syn/asyn) that allows loading of a binary value into the counter FF. • Clear: Asynchronous or Synchronous Reset. • Preset: A Set (Syn. Or Asyn.). • Counter Enable: A Control Function that allows a counter to count the sequences or disable the count. • BiDirectional: A Control line to switch counter from a Count Up to Count Down.

  21. Parallel Load Counter(4 Bit) I • A Preset Counter (Parallel Load) has an additional input (Load) that can be synchronous or asynchronous and four parallel Data Inputs

  22. Synchronous Load Counter I Fig. 9.23 Fig. 9.24

  23. Synchronous Load Counter II Fig. 9.25 Counter Element with Synchronous Load/ Asynchronous Reset (sl_count)

  24. Synchronous Load Counter III Fig. 9.26 4-bit counter with synchronous load and asynchronous reset Refer to Fig. 9.27 Simulation results

  25. Asynchronous Load Counter I Fig. 9.29 Fig. 9.30 (al_count)

  26. Asynchronous Load Counter II Fig. 9.31

  27. Asynchronous Load Counter III Fig. 9.32 Simulation of a 4-bit counter with asynchronous load and reset

  28. Count Enable Logic I Fig. 9.33

  29. Count Enable Logic II Fig. 9.34 Simulation of a 4-bit counter with synchronous load, asynchronous reset, and count enable

  30. Bidirectional Counter I(using T-FF) • Adds a Direction Input(DIR) to the counter and the Control Logic for Up or Down Counting. Fig. 9.37 Synchronous counter element(T-FF)

  31. Bidirectional Counter (Fig. 9.38)

  32. Bidirectional Counter II Fig. 9.39 Simulation of 4-bit bidirectional counter

  33. Decoding the Output of a Counter Fig. 9.40

  34. 4-to-16 Decoder VHDL Code

  35. 4-to-16 Decoder Simulation

  36. Terminal Count Decoder

  37. 4-bit Bidirectional Counter with RCO

  38. Simulation of a 4-bit Bidirectional Counter with RCO

  39. -- 8-bit presettable counter with asynchronous clear and load and terminal count decoding ENTITY pre_ct8a IS PORT( clk, count_ena : IN BIT; clear, load, direction : IN BIT; p : ININTEGER RANGE 0 TO 255; max_min : OUT BIT; qd : OUT INTEGER RANGE 0 TO 255); END pre_ct8a; ARCHITECTURE a OF pre_ct8a IS BEGIN PROCESS (clk, clear, load) -- clear and load are asynchronous and independent on clock VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clear = '0') THEN -- Asynchrnous clear, clear is firstly checked because of the highest priority cnt := 0; ELSIF (load = '1' and clear = '1') THEN -- Asynchronous load, the second priority cnt := p; ELSE IF (clk'EVENT AND clk = '1') THEN IF (count_ena = '1' and direction = '0') THEN cnt := cnt - 1; ELSIF (count_ena = '1' and direction = '1') THEN cnt := cnt + 1; END IF; END IF; END IF; qd <= cnt; -- Terminal count decoder IF (cnt = 0 and direction = '0') THEN max_min <= '1'; ELSIF (cnt = 255 and direction = '1') THEN max_min <= '1'; ELSE max_min <= '0'; END IF; END PROCESS; END a;

  40. -- 8-bit presettable counter with synchronous clear and load and terminal count decoding ENTITY pre_ct8s IS PORT( clk, count_ena : IN BIT; clear, load, direction : IN BIT; p : IN INTEGER RANGE 0 TO 255; max_min : OUT BIT; q : OUT INTEGER RANGE 0 TO 255); END pre_ct8s; ARCHITECTURE a OF pre_ct8s IS BEGIN PROCESS (clk) VARIABLE cnt : INTEGER RANGE 0 TO 255; BEGIN IF (clk'EVENT AND clk = '1') THEN IF (clear = '0') THEN -- Synchronous clear cnt := 0; ELSIF (load = '1') THEN -- Synchronous load cnt := p; ELSIF (count_ena = '1' and direction = '0') THEN cnt := cnt - 1; ELSIF (count_ena = '1' and direction = '1') THEN cnt := cnt + 1; END IF; END IF; qd <= cnt; -- Terminal count decoder IF (cnt = 0 and direction = '0') THEN max_min <= '1'; ELSIF (cnt = 255 and direction = '1') THEN max_min <= '1'; ELSE max_min <= '0'; END IF; END PROCESS; END a;

  41. 8-bit Birectional Counter RCO

  42. LPM Counter

  43. LPM Counter Example I – 8-bit updown counter

  44. LPM Counter Example II – Mod-500 up-counter

  45. LPM Counter Example III – 12-bit counter with sset

  46. LPM Counter Example III – Sim. of a 12-bit counter with sset

  47. Shift Register Terminology • Shift Register: A Synchronous Sequential circuit that will store and move N-bit data either serially or in parallel in a N-Bit Register(FF). • Left Shift: A movement of data from right to left in the shift register(towards the MSB). One bit shift per clock pulse. • Right Shift: A movement of data from left to right in the shift register(towards the LSB). One bit shift per clock pulse. • Rotation: Serial Shifting(Right or Left) with the Output of the last FF connected to the Input of the first. Results in continuous circulation of SR data. Fig. 9.57

  48. BiDirectional Shift Register

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