1 / 17

Implementing a 1024-bit RSA on FPGA

Implementing a 1024-bit RSA on FPGA. Jing Lu Qian Wan. Outline. Motivation System Architecture Implementation Testing. Motivation. Network hosts and devices are threatened by virus, worms, and all sorts of attacks

kioko
Download Presentation

Implementing a 1024-bit RSA on FPGA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Implementing a 1024-bit RSA on FPGA Jing Lu Qian Wan

  2. Outline • Motivation • System Architecture • Implementation • Testing

  3. Motivation • Network hosts and devices are threatened by virus, worms, and all sorts of attacks • vulnerability of common software applications or lack of secure control and protection mechanisms. • Networking applications using reconfigurable hardware devices become popular • Low cost, high performance and flexibility, and immunity to worms and virus. • Applications include extensible network routers, firewalls, and Internet-enable sensors, etc.

  4. Motivation • These devices are distributed in a large geographic area and operate over public networks • Robust security mechanisms for remote control and configuration are highly needed. • RSA algorithm is a secure, high quality, public key algorithm. It can be used in these applications as a method for exchanging secret information such as secret keys and source authentication.

  5. Motivation • Design Goal • WORK (optimize it later) • High system frequency • Short critical path • Small area • Reuse modules • No pipeline • Low power • Compute only when needed • Reasonable high throughput • Slow key generation • Fast encryption and decryption

  6. System Architecture Key Generation Select p, q p, q both prime, pq Calculate n = pq Calculate (n) = (p-1)(q-1) Select integer e gcd((n),e) = 1; 1<e< (n) Calculate d Public key KU = {e, n} Private key KR = {d, n} Encryption Plaintext : M < n Ciphertext: C = Me (mod n) Decryption Ciphertext: C Plaintext: M = Cd (mod n)

  7. Primality Test gcd((n),e) n = pq (n) = (p-1) (q-1) e, d n System Architecture • Key Generation Random Number Generator

  8. n e, d Modular Exponentiation m C System Architecture • Encryption

  9. n e, d Modular Exponentiation C m System Architecture • Decryption

  10. Implementation • Pseudo Random Number Generator • LFSR (Fibonacci configuration) • Length of the pseudo-random sequence depends on the length of the shift register and the number and position of the feedback taps.

  11. Implementation • 512-bit Random Number Generator RNG 512 seed ce 512 output reset_l clk

  12. Implementation • Modular Arithmetic • Modular Addition • concatenate 32-bit full adders • Modular Multiplication • binary method • Modular Exponentiation • binary method

  13. Implementation • Addition • 16 clock latency for 512-bit adder • 32 clock latency for 1024-bit adder 512 a 512-bit adder ready 512 b s_valid c_in 512 s start c_out reset_l clk

  14. Implementation • Modular Multiplication (512 bits and 1024 bits) 512 a 512-bit mod_mul 512 b ready 512 n m_valid start 512 m reset_l clk

  15. Implementation • Modular Exponentiation (512 bits and 1024 bits) 512 a 512-bit mod_exp 512 b ready 512 n e_valid start 512 e reset_l clk

  16. Request KU Testing

  17. KU(m) KR(KU(m)) Testing

More Related