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5.5 VDHL 程序设计实例

5.5 VDHL 程序设计实例. 组合逻辑是电路设计的基础 , 常见的组合逻辑电路是编码器、译码器、多路选择器、数据选择器、加法器等。. 5.5.1 常用组合电路的设计. 组合逻辑的描述可通过并行信号赋值语句或纯粹组合逻辑行为的进程语句来实现。. 并行赋值语句： 1 、简单信号赋值语句 2 、条件信号赋值语句 3 、选择信号赋值语句 进程语句： 为了保证一个进程语句能生成组合逻辑，在进程语句里所有被读入的信号都必须包含在该进程语句的敏感表中。. a. y. &. b. 图 5.4.1 二输入与门. 5.5.1.1 门电路. 1 、与门.

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5.5 VDHL 程序设计实例

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  1. 5.5 VDHL程序设计实例 组合逻辑是电路设计的基础,常见的组合逻辑电路是编码器、译码器、多路选择器、数据选择器、加法器等。 5.5.1 常用组合电路的设计 组合逻辑的描述可通过并行信号赋值语句或纯粹组合逻辑行为的进程语句来实现。 并行赋值语句： 1、简单信号赋值语句 2、条件信号赋值语句 3、选择信号赋值语句 进程语句： 为了保证一个进程语句能生成组合逻辑，在进程语句里所有被读入的信号都必须包含在该进程语句的敏感表中。

  2. a y & b . . 图5.4.1 二输入与门 5.5.1.1 门电路 1、与门 【程序5.4.1】 library ieee; use ieee.std_logic_1164.all; entity and2 is port (a : in std_logic; b : in std_logic; y : out std_logic ); end and2; architecture behave of and2 is begin y<=a and b; end behave; 表5.4.1 二输入与门真值表

  3. a y & b . . 图5.4.1 二输入与门 【程序5.4.2】 library ieee; use ieee.std_logic_1164.all; entity and2 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end and2; architecture rtl of and2 is begin p1:process(a,b) variable comb : std_logic_vector (1downto 0); begin comb:= a&b; case comb is when "00" =>y<='0'; when "10"=>y<='0'; when "01" =>y<='0'; when "11" =>y<='1'; when others =>y<='X'; end case; end process p1; end rtl; 表5.4.1 二输入与门真值表

  4. a y ≥1 b . . 图5.4.2 二输入或门 2、或门 【程序5.4.3】 library ieee; use ieee.std_logic_1164.all; entity or2 is port (a : in std_logic; b : in std_logic; y : out std_logic ); end and2; architecture behave of and2 is begin y<=a or b; end behave; 表5.4.2 二输入或门真值表

  5. a y ≥1 b . . 图5.4.2 二输入或门 【程序5.4.4】 library ieee; use ieee.std_logic_1164.all; entity or2 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end and2; architecture rtl of or2 is begin p1:process(a,b) variable comb : std_logic_vector (1downto 0); begin comb:= a&b; case comb is when "00" =>y<='0'; when "10"=>y<='1'; when "01" =>y<='1'; when "11" =>y<='1'; when others =>y<='X'; end case; end process p1; end rtl; 表5.4.2 二输入或门真值表

  6. 1 a y 图5.4.3 反相器电路 3.反相器 【程序5.4.5】 library ieee; use ieee.std_logic_1164.all; entity not2 is port ( a : in std_logic ; y : out std_logic ); end not2; architecture behave of not2 is begin y <= not a; end behave; 表5.4.3 反相器真值表

  7. 1 a y 图5.4.3 反相器电路 【程序5.4.6】 library ieee; use ieee.std_logic_1164.all; entity not2 is port ( a，b : in std_logic ; y : out std_logic ); end not2; architecture rtl of not2 is begin p1:process(a,b) begin if (a='1') then y<='0'; else y<='1'; end if; end process p1; end rtl; 表5.4.3 反相器真值表

  8. a & y b 图5.4.4 二输入与非门 4.与非门 【程序5.4.7】 library ieee; use ieee.std_logic_1164.all; entity nand2 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end nand2; architecture behave of nand2 is begin y<=a nand b; end behave; 表5.4.4 二输入与非门真值表

  9. a & y b 图5.4.4 二输入与非门 【程序5.4.8】 ………….. architecture rtl of nand2 is begin p1:process(a,b) variable comb : std_logic_vector (1downto 0); begin comb:= a&b; case comb is when "00" =>y<= '1'; when "10" =>y<= '1'; when "01" =>y<= '1'; when "11" =>y<= '0'; when others =>y<='X'; end case; end process p1; end rtl; 表5.4.4 二输入与非门真值表

  10. a ≥1 y b 图5.4.5 二输入或非门 5.或非门 【程序5.4.9】 library ieee; use ieee.std_logic_1164.all; entity nor2 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end nor2; architecture behave of nor2 is begin y<=a nor b; end behave; 表5.4.5 二输入或非门真值表

  11. a ≥1 y b 图5.4.5 二输入或非门 【程序5.4.10】 ………….. architecture rtl of nor2 is begin p1:process(a,b) variable comb : std_logic_vector (1downto 0); begin comb:= a&b; case comb is when "00" =>y<= '0'; when "10" =>y<= '0'; when "01" =>y<= '0'; when "11" =>y<= '1'; when others =>y<='X'; end case; end process p1; end rtl; 表5.4.5 二输入或非门真值表

  12. a ＝1 y b 图5.4.6 二输入异或门 6.异或门 【程序5.4.11】 library ieee; use ieee.std_logic_1164.all; entity xor2 is port ( a : in std_logic; b : in std_logic; y : out std_logic); end xor2; architecture behave of xor2 is begin y<=a xor b; end behave; 表5.4.6 二输入异或门真值表

  13. a ＝1 y b 图5.4.6 二输入异或门 【程序5.4.12】 ………….. architecture rtl of xor2 is begin p1:process(a,b) variable comb : std_logic_vector (1downto 0); begin comb:= a&b; case comb is when "00" =>y<= '0'; when "10" =>y<= '1'; when "01" =>y<= '1'; when "11" =>y<= '0'; when others =>y<='X'; end case; end process p1; end rtl; 表5.4.6 二输入异或门真值表

  14. d0 8－3 编码器 q0 d1 d2 d3 q1 d4 d5 d6 q2 d7 5.5.1.2 编码器与译码器 architecture rtl of coder is begin p1:process (d) begin case d is when"01111111"=>q<="111"; when"10111111"=>q<="110"; when"11011111"=>q<="101"; when"11101111"=>q<="100"; when "11110111"=>q<="011"; when"11111011"=>q<="010"; when"11111101"=>q<="001"; when"11111110"=>q<="000"; when others=>null; end case; end process p1; end rtl; 8线－3线编码器 图5.4.7 8－3线编码器 【程序5.4.13】 library ieee; use ieee.std_logic_1164.all； entity coder is port ( d: in std_logic_vector(7 downto 0); q: out std_logic_vector(2 downto 0)); end coder;

  15. 分析下面程序并指出其实现何种功能： 【程序】 library ieee; use ieee.std_logic_1164.all; entity decoder is port( data_in : in std_logic_vector(2 downto 0); G1,G2A,G2B : in std_logic; d : out std_logic_vector(7 downto 0)); end entity decoder; architecture rtl of decoder is begin p1：process (data_in, G1,G2A,G2B) 接下页

  16. begin d <= (others => ‘1'); if ( G1='1' and G2A='0' and G2B='0') then case data_in_TEMP is when"000" => d(7 downto 0) <= "00000001"; when"001" => d(7 downto 0) <= "00000010"; when"010" => d(7 downto 0) <= "00000100"; when"011" => d(7 downto 0) <= "00001000"; when"100" => d(7 downto 0) <= "00010000"; when"101" => d(7 downto 0) <= "00100000"; when"110" => d(7 downto 0) <= "01000000"; when"111" => d(7 downto 0) <= "10000000"; when others => d <= (others => '0'); end case; end if; end process p1; end rtl; 3－8线译码器

  17. a 4-1 MUX b y c d s 5 . 4 . 9 4选1数据选择器 5.5.1.3 数据选择器 【程序5.4.16】 library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic_vector(3 downto 0)); end mux; architecture archmux of mux is begin mux4_1: process (a, b, c, d) begin if s = "00"then y <= a; elsif s = "01"then y <= b; elsif s = "10"then y <= c; else y <= d; end if; end process mux4_1; end archmux; 表5.4.9 真值表

  18. a0 Bt a1 a2 CC14585 a3 St b0 b1 EQ b2 b3 i1 i2 i3 图5.4.10 四位数据比较器 5.5.1.4 数据比较器 四位数值比较器CC14585的工作原理 : 表5.4.10 CC14585的真值表

  19. CC14585 a0 Bt a1 a2 a3 St 图5.4.10 四位数据比较器 b0 b1 EQ b2 b3 i1 i2 i3 【程序5.4.17】 library ieee; use ieee.std_logic_1164.all； entity cc14585 is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); i1,i2,i3 : in std_logic; bt, st, eq : out std_logic); end cc14585; architecture behave of cc14585 is begin p1 : process (a,b,i1,i2,i3); begin if (a>b) then bt<='1';eq<='0';st<='0'; elsif (a<b) then bt<='0';eq<='0';st<='1'; elsif (a=b) then if (i2='1') then bt<='0';eq<='1';st<='0'; elsif (i1='1') then bt<='1';eq<='0';st<='0'; elsif (i3='1') then bt<='0';eq<='0';st<='1'; end if; end if; end process p1; end behave;

  20. 5.5.1.5 加法器 【程序5.4.18】 library ieee; use ieee.std_logic_1164.all; entity adderN is generic (N : integer := 16); port (a : in std_logic_vector(N downto 1); b : in std_logic_vector(N downto 1); cin : in std_logic; sum : out std_logic_vector(N downto 1); cout : out std_logic); end adderN;

  21. architecture structural of adderN is component adder port (a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; cout : out std_logic); end component; signal carry : std_logic_vector(0 to N); begin carry(0) <= cin; cout <= carry(N); gen: for i in 1 to N generate add: adder port map(a => a(i),b => b(i),cin => carry(i - 1), sum => sum(i),cout => carry(i)); end generate; end structural;

  22. architecture behavioral of adderN is begin p1: process(a, b, cin) variable vsum : std_logic_vector(N downto 1); variable carry : std_logic; begin carry := cin; for i in 1 to N loop vsum(i) := (a(i) xor b(i)) xor carry; carry := (a(i) and b(i)) or (carry and (a(i) or b(i))); end loop; sum <= vsum; cout <= carry; end process p1; end behavioral;

  23. 5.5.2 常用时序电路的设计 组合逻辑电路在任一时刻的输出仅仅取决于该时刻电路的输入，和电路原来的状态无关。与之相反，时序电路不仅与电路的输入有关，而且与电路原状态有关。时序逻辑电路的特点是包含一个或多个的寄存器。 x1 Y1 xn Ym qs …q1 Z1 … Zr 图中，x1 ~ xn 为时序电路输入信号， 又称组合电路外部输入。Z1 ~ Zm为时序电路输出信号，又称组合电路外部输出。 y1 ~ ys 为时序电路的 “状态” 信号，又称组合电路内部输入。Y1 ~Yr为时序电路激励信号，又称组合电路内部输出。 ： ： 组合电路 存储电路 时钟 CP 某一时刻的状态称为 “现态”，记作 y，某一现态下随外部信号变化而即将到达的状态称为 “次态”，记作 y(n+1)。

  24. 常用的时序电路包括： 触发器、寄存器、移位寄存器、计数器、存储器等 任何时序电路都是以时钟为驱动信号，时序电路只是在时钟信号的边沿来到时才会发生状态的改变。 时序逻辑的实现通常使用 process 语句来实现。

  25. wait on （clock_signal） until (clock_signal_condition); 此时，描述时序电路的进程将没有敏感信号。 5.5.2.1 时钟及复位信号的处理 1. 进程的敏感信号 process (clock_signal) Begin if (clock_edge_condiition) then signal_out <=signal_in; … … end if; end process; • 在敏感信号的表中只能出现一个时钟信号；但是，复位信号等与时钟信号可以出现在敏感信号表中。 • 在if语句中注明时钟是上升沿还是下降沿。 以上升沿为例说明表述方式。 表述方式1：if clk'event and clk_last_value='0' and clk='1' if clk'event and clk= '1' 表述方式2：if（rising_edge(clk)) 2. 用进程中的wait on语句等待时钟

  26. 3. 同步和非同步复位 同步/异步时序电路区别：有无统一的时钟脉冲控制。 ① 同步复位：当复位信号有效且在约定的时钟边沿到来时触发器才被复位。 process (clk) --敏感信号只有时钟信号 Begin if (clock_edge_condition) then if (reset) then signal_out<=reset_value;--嵌套的if语句 else… … end if; end if； end process; ②非同步复位： --敏感信号中包括reset信号 process (reset,clk) Begin if (reset) then signal_out<=reset_value; elsif (clock_edge_condition) then … … end if； End process; --复位信号 --时钟边沿

  27. 5.5.2.2 触发器设计 1. D触发器 ① D触发器 【程序5.4.19】 library ieee; use ieee.std_logic_1164.all； entity dff1 is port (clk,d : in std_logic; q : out std_logic ); end dff1; architectrue rtl of dff1 is begin process (clk) begin if (clk'event and clk='1') then q<=d; end if; end process; end rtl;

  28. clk q d clr ② 非同步复位的D触发器 library ieee; use ieee.std_logic_1164.all entity dff2 is port (clk,d,clr : in std_logic; q : out std_logic ); end dff2; architecture rtl of dff2 is begin process (clk,clr) begin if (clr='0') then q<='0'; elsif (clk'event and clk='1') then q<=d; end if; end process; end rtl;

  29. clk q d ≥ d clr ③ 同步复位的D触发器 library ieee; use ieee.std_logic_1164.all; entity dff2 is port (clk,d,clr : in std_logic; q : out std_logic ); end dff3; architecture rtl of dff3 is begin process (clk) begin if (clk’event and clk='1') then if (clr='1') then q<='0'; else q<=d; end if; end if; end process; end rtl;

  30. 2.JK触发器 表5.4.12 Jk触发器的真值表

  31. 5.5.2.3 寄存器设计 1. 普通寄存器 library ieee; use ieee.std_logic_1164.all; entity register is port ( d : in std_logic_vetor(7 downto 0); oe : in std_logic; clk : in std_logic; q : out std_logic_vector(7downto 0)); end register;

  32. architecture rtl of register is signal q_tmp : std_logic_vetor(7downto 0); begin process (clk,oe) begin if (oe='0') then if (clk'event and clk='1') then q_tmp<=d; end if; else q_tmp<="ZZZZZZZZ"; end if; q<=q_tmp; end process; end rtl;

  33. 2. 移位寄存器74LS164 【程序5.4.24】 library ieee; use ieee.std_logic_1164.all; entity dev164 is port(a, b, nclr, clock : in bit; q : buffer bit_vector(0 to 7)); end dev164;

  34. architecture version1 of dev164 is begin process (a,b,nclr,clock) begin if nclr = '0' then q <= "00000000"; elseif clock'event and clock = '1' then for i in q'range loop if (i = 0) then q(i) <= (a and b); else q(i) <= q(i-1); end if; end loop; end if; end if; end process; end version1;

  35. 5.5.2.4 计数器设计 通常将计数器可分为以下几类： • 按照计数器中的触发器是否同时翻转分类： 同步计数器和异步计数器 • 按照计数过程中的数字增减分类： 加法计数器、减法计数器、可逆计数器 • 按照计数器中数字和编码方式分类： 二进制、二-十进制、循环计数器 • 按照计数器的容量： 十进制计数器、十二进制计数器、六十进制计数器

  36. 【程序5.4.26】 library ieee; use ieee.std_logic_1164.all; entity counter is port ( d : in integer range 0 to 255; clk,clear,ld : in std_logic; enable,up_down : in std_logic; qa, qb, qc, qd, qe : out integer range 0 to 255; qf, qg, qh, qi, qj : out integer range 0 to 255; qk, ql, qm, qn : out integer range 0 to 255 ); end counter; architecture behave of counter is begin

  37. P1: process( clk ) variable cnt: integer range 0 to 255; begin if（clk’event and clk = ‘1’）then if（enable = ‘1’）then cnt ：= cnt + 1; end if; end if; qa <= cnt; end process; --8位同步受控计数器

  38. P4-1: process( clk ) variable cnt: integer range 0 to 255:=0; variable direction: integer; begin if up_down = ‘1’ then direction := 1; else direction := -1; end if ; if clk’event and clk = ‘1’ then cnt := cnt + direction; end if; qd <= cnt; end process; －－同步可逆计数器

  39. P4-2: process( clk ) variable cnt: integer range 0 to 255 :=0; begin if clk’event and clk = ‘1’ then if up_down = ‘1’ then cnt := cnt + 1; else cnt := cnt – 1; end if; end if; qd <= cnt; end process;

  40. P14: process( clk ) variable cnt: integer range 0 to 255:=0; constant modulus: integer:=199; begin if (clk’event and clk = ‘1’) then if cnt = modulus then cnt := 0; else cnt := cnt + 1; end if; end if; qn <= cnt; end process; 模数为200的计数器 设计一个带有异步复位端和计数使能端的10进制计数器？

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